xref: /rk3399_ARM-atf/plat/mediatek/mt8173/plat_mt_gic.c (revision 9a207532f8216bf83fed0891fed9ed0bc72ca450)
17d116dccSCC Ma /*
2ed81f3ebSSandrine Bailleux  * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
37d116dccSCC Ma  *
482cb2c1aSdp-arm  * SPDX-License-Identifier: BSD-3-Clause
57d116dccSCC Ma  */
6b8424642SAntonio Nino Diaz 
7*09d40e0eSAntonio Nino Diaz #include <common/bl_common.h>
8*09d40e0eSAntonio Nino Diaz #include <lib/utils.h>
9*09d40e0eSAntonio Nino Diaz 
107d116dccSCC Ma #include <mt8173_def.h>
117d116dccSCC Ma 
127d116dccSCC Ma const unsigned int mt_irq_sec_array[] = {
137d116dccSCC Ma 	MT_IRQ_SEC_SGI_0,
147d116dccSCC Ma 	MT_IRQ_SEC_SGI_1,
157d116dccSCC Ma 	MT_IRQ_SEC_SGI_2,
167d116dccSCC Ma 	MT_IRQ_SEC_SGI_3,
177d116dccSCC Ma 	MT_IRQ_SEC_SGI_4,
187d116dccSCC Ma 	MT_IRQ_SEC_SGI_5,
197d116dccSCC Ma 	MT_IRQ_SEC_SGI_6,
207d116dccSCC Ma 	MT_IRQ_SEC_SGI_7
217d116dccSCC Ma };
227d116dccSCC Ma 
plat_mt_gic_init(void)237d116dccSCC Ma void plat_mt_gic_init(void)
247d116dccSCC Ma {
257d116dccSCC Ma 	arm_gic_init(BASE_GICC_BASE,
267d116dccSCC Ma 		BASE_GICD_BASE,
277d116dccSCC Ma 		BASE_GICR_BASE,
287d116dccSCC Ma 		mt_irq_sec_array,
297d116dccSCC Ma 		ARRAY_SIZE(mt_irq_sec_array));
307d116dccSCC Ma }
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