37 	 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x4),  in mt_irq_mask_restore()
39 	 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x8),  in mt_irq_mask_restore()
41 	 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0xc),  in mt_irq_mask_restore()
43 	 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x10),  in mt_irq_mask_restore()
45 	 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x14),  in mt_irq_mask_restore()
47 	 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x18),  in mt_irq_mask_restore()
49 	 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x1c),  in mt_irq_mask_restore()
51 	 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x20),  in mt_irq_mask_restore()
53 	 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x24),  in mt_irq_mask_restore()
55 	 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x28),  in mt_irq_mask_restore()
57 	 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x2c),  in mt_irq_mask_restore()
59 	 mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x30),  in mt_irq_mask_restore()
77 		mask->mask1 = mmio_read_32((BASE_GICD_BASE +  in mt_irq_mask_all()
79 		mask->mask2 = mmio_read_32((BASE_GICD_BASE +  in mt_irq_mask_all()
81 		mask->mask3 = mmio_read_32((BASE_GICD_BASE +  in mt_irq_mask_all()
83 		mask->mask4 = mmio_read_32((BASE_GICD_BASE +  in mt_irq_mask_all()
85 		mask->mask5 = mmio_read_32((BASE_GICD_BASE +  in mt_irq_mask_all()
87 		mask->mask6 = mmio_read_32((BASE_GICD_BASE +  in mt_irq_mask_all()
89 		mask->mask7 = mmio_read_32((BASE_GICD_BASE +  in mt_irq_mask_all()
91 		mask->mask8 = mmio_read_32((BASE_GICD_BASE +  in mt_irq_mask_all()
93 		mask->mask9 = mmio_read_32((BASE_GICD_BASE +  in mt_irq_mask_all()
95 		mask->mask10 = mmio_read_32((BASE_GICD_BASE +  in mt_irq_mask_all()
97 		mask->mask11 = mmio_read_32((BASE_GICD_BASE +  in mt_irq_mask_all()
99 		mask->mask12 = mmio_read_32((BASE_GICD_BASE +  in mt_irq_mask_all()
103 		mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x4),  in mt_irq_mask_all()
105 		mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x8),  in mt_irq_mask_all()
107 		mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0xC),  in mt_irq_mask_all()
109 		mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x10),  in mt_irq_mask_all()
111 		mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x14),  in mt_irq_mask_all()
113 		mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x18),  in mt_irq_mask_all()
115 		mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x1C),  in mt_irq_mask_all()
117 		mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x20),  in mt_irq_mask_all()
119 		mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x24),  in mt_irq_mask_all()
121 		mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x28),  in mt_irq_mask_all()
123 		mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x2c),  in mt_irq_mask_all()
125 		mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x30),  in mt_irq_mask_all()
303 	addr = BASE_GICD_BASE + GICD_ISENABLER + (irq / 32U) * 4U;  in mt_irq_get_en()
393 	base = BASE_GICD_BASE;  in mt_irq_get_pending_vec()
482 	mmio_write_32(BASE_GICD_BASE + GICD_ISENABLER +  in mt_irq_unmask_for_sleep_ex()