16fba6e04STony Xie /* 2*ed7a5636SDeepika Bhavnani * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 36fba6e04STony Xie * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 56fba6e04STony Xie */ 66fba6e04STony Xie 71083b2b3SAntonio Nino Diaz #ifndef PLATFORM_DEF_H 81083b2b3SAntonio Nino Diaz #define PLATFORM_DEF_H 96fba6e04STony Xie 106fba6e04STony Xie #include <arch.h> 1109d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 1209d40e0eSAntonio Nino Diaz #include <plat/common/common_def.h> 1309d40e0eSAntonio Nino Diaz 14ae7a9352SXing Zheng #include <bl31_param.h> 156fba6e04STony Xie #include <rk3399_def.h> 166fba6e04STony Xie 176fba6e04STony Xie /******************************************************************************* 186fba6e04STony Xie * Platform binary types for linking 196fba6e04STony Xie ******************************************************************************/ 206fba6e04STony Xie #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 216fba6e04STony Xie #define PLATFORM_LINKER_ARCH aarch64 226fba6e04STony Xie 236fba6e04STony Xie /******************************************************************************* 246fba6e04STony Xie * Generic platform constants 256fba6e04STony Xie ******************************************************************************/ 266fba6e04STony Xie 276fba6e04STony Xie /* Size of cacheable stacks */ 282d6f1f01SAntonio Nino Diaz #if defined(IMAGE_BL1) 296fba6e04STony Xie #define PLATFORM_STACK_SIZE 0x440 303d8256b2SMasahiro Yamada #elif defined(IMAGE_BL2) 316fba6e04STony Xie #define PLATFORM_STACK_SIZE 0x400 323d8256b2SMasahiro Yamada #elif defined(IMAGE_BL31) 336fba6e04STony Xie #define PLATFORM_STACK_SIZE 0x800 343d8256b2SMasahiro Yamada #elif defined(IMAGE_BL32) 356fba6e04STony Xie #define PLATFORM_STACK_SIZE 0x440 366fba6e04STony Xie #endif 376fba6e04STony Xie 386fba6e04STony Xie #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 396fba6e04STony Xie 406fba6e04STony Xie #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 41*ed7a5636SDeepika Bhavnani #define PLATFORM_SYSTEM_COUNT U(1) 42*ed7a5636SDeepika Bhavnani #define PLATFORM_CLUSTER_COUNT U(2) 43*ed7a5636SDeepika Bhavnani #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 44*ed7a5636SDeepika Bhavnani #define PLATFORM_CLUSTER1_CORE_COUNT U(2) 456fba6e04STony Xie #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 466fba6e04STony Xie PLATFORM_CLUSTER0_CORE_COUNT) 47*ed7a5636SDeepika Bhavnani #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 486fba6e04STony Xie #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 496fba6e04STony Xie PLATFORM_CLUSTER_COUNT + \ 506fba6e04STony Xie PLATFORM_CORE_COUNT) 519ec78bdfSTony Xie #define PLAT_RK_CLST_TO_CPUID_SHIFT 6 526fba6e04STony Xie #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 536fba6e04STony Xie 546fba6e04STony Xie /* 556fba6e04STony Xie * This macro defines the deepest retention state possible. A higher state 566fba6e04STony Xie * id will represent an invalid or a power down state. 576fba6e04STony Xie */ 581083b2b3SAntonio Nino Diaz #define PLAT_MAX_RET_STATE U(1) 596fba6e04STony Xie 606fba6e04STony Xie /* 616fba6e04STony Xie * This macro defines the deepest power down states possible. Any state ID 626fba6e04STony Xie * higher than this is invalid. 636fba6e04STony Xie */ 641083b2b3SAntonio Nino Diaz #define PLAT_MAX_OFF_STATE U(2) 656fba6e04STony Xie 666fba6e04STony Xie /******************************************************************************* 676fba6e04STony Xie * Platform specific page table and MMU setup constants 686fba6e04STony Xie ******************************************************************************/ 692d6f1f01SAntonio Nino Diaz #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 702d6f1f01SAntonio Nino Diaz #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 716fba6e04STony Xie #define MAX_XLAT_TABLES 20 729ec78bdfSTony Xie #define MAX_MMAP_REGIONS 25 736fba6e04STony Xie 746fba6e04STony Xie /******************************************************************************* 756fba6e04STony Xie * Declarations and constants to access the mailboxes safely. Each mailbox is 766fba6e04STony Xie * aligned on the biggest cache line size in the platform. This is known only 776fba6e04STony Xie * to the platform as it might have a combination of integrated and external 786fba6e04STony Xie * caches. Such alignment ensures that two maiboxes do not sit on the same cache 796fba6e04STony Xie * line at any cache level. They could belong to different cpus/clusters & 806fba6e04STony Xie * get written while being protected by different locks causing corruption of 816fba6e04STony Xie * a valid mailbox address. 826fba6e04STony Xie ******************************************************************************/ 836fba6e04STony Xie #define CACHE_WRITEBACK_SHIFT 6 846fba6e04STony Xie #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 856fba6e04STony Xie 866fba6e04STony Xie /* 876fba6e04STony Xie * Define GICD and GICC and GICR base 886fba6e04STony Xie */ 896fba6e04STony Xie #define PLAT_RK_GICD_BASE BASE_GICD_BASE 906fba6e04STony Xie #define PLAT_RK_GICR_BASE BASE_GICR_BASE 916fba6e04STony Xie #define PLAT_RK_GICC_BASE 0 926fba6e04STony Xie 931830f790SXing Zheng #define PLAT_RK_UART_BASE UART2_BASE 946fba6e04STony Xie #define PLAT_RK_UART_CLOCK RK3399_UART_CLOCK 956fba6e04STony Xie #define PLAT_RK_UART_BAUDRATE RK3399_BAUDRATE 966fba6e04STony Xie 976fba6e04STony Xie #define PLAT_RK_CCI_BASE CCI500_BASE 986fba6e04STony Xie 996fba6e04STony Xie #define PLAT_RK_PRIMARY_CPU 0x0 1006fba6e04STony Xie 101bc5c3007SLin Huang #define PSRAM_DO_DDR_RESUME 1 10284597b57SLin Huang #define PSRAM_CHECK_WAKEUP_CPU 0 10384597b57SLin Huang 1041083b2b3SAntonio Nino Diaz #endif /* PLATFORM_DEF_H */ 105