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/optee_os/core/arch/arm/dts/
H A Dstm32mp23-st-scmi-cfg.dtsi9 #include <dt-bindings/scmi/scmi-clock.h>
32 clock@0 {
38 clock@1 {
44 clock@2 {
50 clock@3 {
56 clock@4 {
62 clock@5 {
68 clock@6 {
74 clock@7 {
80 clock@8 {
[all …]
H A Dstm32mp25-st-scmi-cfg.dtsi9 #include <dt-bindings/scmi/scmi-clock.h>
32 clock@0 {
38 clock@1 {
44 clock@2 {
50 clock@3 {
56 clock@4 {
62 clock@5 {
68 clock@6 {
74 clock@7 {
80 clock@8 {
[all …]
H A Dstm32mp21-st-scmi-cfg.dtsi9 #include <dt-bindings/scmi/scmi-clock.h>
32 clock@0 {
38 clock@1 {
44 clock@2 {
50 clock@3 {
56 clock@4 {
62 clock@5 {
68 clock@7 {
74 clock@8 {
80 clock@9 {
[all …]
H A Dstm32mp211.dtsi6 #include <dt-bindings/clock/st,stm32mp21-rcc.h>
49 #clock-cells = <0>;
50 compatible = "fixed-clock";
51 clock-frequency = <48000000>;
55 #clock-cells = <0>;
56 compatible = "fixed-clock";
57 clock-frequency = <64000000>;
61 #clock-cells = <0>;
62 compatible = "fixed-clock";
63 clock-frequency = <32768>;
[all …]
H A Dsama7g5.dtsi11 #include <dt-bindings/clock/at91.h>
34 clock-names = "cpu";
46 clock-latency-ns = <320000>;
52 clock-latency-ns = <320000>;
58 clock-latency-ns = <320000>;
65 clock-latency-ns = <320000>;
71 clock-latency-ns = <320000>;
115 compatible = "fixed-clock";
116 #clock-cells = <0>;
120 compatible = "fixed-clock";
[all …]
H A Dsama5d2.dtsi11 #include <dt-bindings/clock/at91.h>
36 clock-names = "cpu";
50 clock-names = "apb_pclk";
66 clock-names = "apb_pclk";
84 compatible = "fixed-clock";
85 #clock-cells = <0>;
86 clock-frequency = <0>;
90 compatible = "fixed-clock";
91 #clock-cells = <0>;
92 clock-frequency = <0>;
[all …]
H A Dstm32mp131.dtsi7 #include <dt-bindings/clock/stm32mp13-clks.h>
8 #include <dt-bindings/clock/stm32mp13-clksrc.h>
27 clock-names = "cpu";
82 #clock-cells = <0>;
83 compatible = "fixed-clock";
84 clock-frequency = <24000000>;
88 #clock-cells = <0>;
89 compatible = "fixed-clock";
90 clock-frequency = <64000000>;
94 #clock-cells = <0>;
[all …]
H A Dstm32mp231.dtsi7 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
49 #clock-cells = <0>;
50 compatible = "fixed-clock";
51 clock-frequency = <24000000>;
55 #clock-cells = <0>;
56 compatible = "fixed-clock";
57 clock-frequency = <64000000>;
61 #clock-cells = <0>;
62 compatible = "fixed-clock";
63 clock-frequency = <32768>;
[all …]
H A Dstm32mp251.dtsi7 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
49 #clock-cells = <0>;
50 compatible = "fixed-clock";
51 clock-frequency = <24000000>;
55 #clock-cells = <0>;
56 compatible = "fixed-clock";
57 clock-frequency = <64000000>;
61 #clock-cells = <0>;
62 compatible = "fixed-clock";
63 clock-frequency = <32768>;
[all …]
H A Dstm32mp151.dtsi7 #include <dt-bindings/clock/stm32mp1-clks.h>
21 clock-frequency = <650000000>;
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <24000000>;
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <64000000>;
70 #clock-cells = <0>;
71 compatible = "fixed-clock";
[all …]
H A Dstm32mp215f-dk-ca35tdcid-rcc.dtsi11 clock-frequency = <40000000>;
15 clock-frequency = <64000000>;
19 clock-frequency = <32768>;
23 clock-frequency = <32000>;
27 clock-frequency = <16000000>;
H A Dstm32mp235f-dk-ca35tdcid-rcc.dtsi7 clock-frequency = <40000000>;
11 clock-frequency = <64000000>;
15 clock-frequency = <32768>;
19 clock-frequency = <32000>;
23 clock-frequency = <16000000>;
H A Dstm32mp153.dtsi13 clock-frequency = <650000000>;
42 clock-names = "hclk", "cclk";
56 clock-names = "hclk", "cclk";
H A Dstm32mp15xx-dhcom-pdk2.dtsi18 clk_ext_audio_codec: clock-codec {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <24000000>;
222 clock-names = "pclk", "x8k", "x11k";
229 #clock-cells = <0>;
232 clock-names = "sai_ck";
250 clock-names = "sai_ck", "MCLK";
H A Dstm32mp257f-dk-ca35tdcid-rcc.dtsi7 clock-frequency = <40000000>;
11 clock-frequency = <64000000>;
15 clock-frequency = <32768>;
19 clock-frequency = <32000>;
23 clock-frequency = <16000000>;
H A Dstm32mp257f-ev1-ca35tdcid-rcc.dtsi7 clock-frequency = <40000000>;
11 clock-frequency = <64000000>;
15 clock-frequency = <32768>;
19 clock-frequency = <32000>;
23 clock-frequency = <16000000>;
H A Dstm32mp157.dtsi16 clock-names = "bus" ,"core";
24 clock-names = "pclk", "ref", "px_clk";
H A Dstm32mp15xx-dhcor-avenger96.dtsi23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <24000000>;
228 clock-names = "cec";
243 adi,input-clock = "1x";
295 clock-names = "pclk", "x8k", "x11k";
299 #clock-cells = <0>;
302 clock-names = "sai_ck";
/optee_os/core/lib/scmi-server/
H A Dscmi_clock_consumer.c30 struct clk *clock; member
161 struct clk *clock = NULL; in optee_scmi_server_init_clocks() local
164 res = clk_dt_get_by_index(fdt, subnode, 0, &clock); in optee_scmi_server_init_clocks()
184 if (s_clock->clock) { in optee_scmi_server_init_clocks()
188 s_clock->clock = clock; in optee_scmi_server_init_clocks()
208 if (!s_clocks[n].clock) { in optee_scmi_server_init_clocks()
218 if (consumer->clocks || channel_cfg->clock) { in optee_scmi_server_init_clocks()
233 channel_cfg->clock = calloc(channel_cfg->clock_count, in optee_scmi_server_init_clocks()
234 sizeof(*channel_cfg->clock)); in optee_scmi_server_init_clocks()
235 assert(channel_cfg->clock); in optee_scmi_server_init_clocks()
[all …]
/optee_os/core/drivers/regulator/
H A Dstm32_vrefbuf.c57 struct clk *clock; member
111 res = clk_enable(vr->clock); in vrefbuf_set_state()
130 clk_disable(vr->clock); in vrefbuf_set_state()
140 clk_disable(vr->clock); in vrefbuf_set_state()
150 res = clk_enable(vr->clock); in vrefbuf_get_state()
156 clk_disable(vr->clock); in vrefbuf_get_state()
168 res = clk_enable(vr->clock); in vrefbuf_get_voltage()
175 clk_disable(vr->clock); in vrefbuf_get_voltage()
192 res = clk_enable(vr->clock); in vrefbuf_set_voltage()
199 clk_disable(vr->clock); in vrefbuf_set_voltage()
[all …]
/optee_os/core/drivers/clk/
H A Dclk-stm32mp15.c737 unsigned long clock = 0; in get_clock_rate() local
746 clock = osc_frequency(OSC_HSI); in get_clock_rate()
749 clock = osc_frequency(OSC_HSE); in get_clock_rate()
752 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); in get_clock_rate()
757 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P) >> in get_clock_rate()
760 clock = 0; in get_clock_rate()
776 clock = osc_frequency(OSC_HSI); in get_clock_rate()
779 clock = osc_frequency(OSC_HSE); in get_clock_rate()
782 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); in get_clock_rate()
790 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; in get_clock_rate()
[all …]
/optee_os/core/arch/arm/plat-stm32mp1/
H A Dscmi_server.c326 struct stm32_scmi_clk *clock; member
355 .clock = stm32_scmi_clock,
509 return &resource->clock[n]; in find_clock()
528 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); in plat_scmi_clock_get_name() local
530 if (!clock || !nsec_can_access_resource(clock->etzpc_id)) in plat_scmi_clock_get_name()
533 return clock->name; in plat_scmi_clock_get_name()
540 struct stm32_scmi_clk *clock = find_clock(channel_id, scmi_id); in plat_scmi_clock_rates_array() local
542 if (!clock) in plat_scmi_clock_rates_array()
545 if (!nsec_can_access_resource(clock->etzpc_id)) in plat_scmi_clock_rates_array()
555 *array = clk_get_rate(clock->clk); in plat_scmi_clock_rates_array()
[all …]
/optee_os/core/drivers/
H A Dstm32_omm.c68 struct clk *clock; member
74 struct clk *clock; member
117 res = clk_dt_get_by_index(fdt, node, 0, &omm_d->clock); in stm32_omm_parse_fdt()
189 res = clk_dt_get_by_index(fdt, ctrl_node, 0, &ospi_d->clock); in stm32_omm_parse_fdt()
256 clk_rate_max = MAX(clk_get_rate(ospi_d->clock), clk_rate_max); in stm32_omm_configure()
258 if (clk_enable(ospi_d->clock)) in stm32_omm_configure()
275 clk_disable(ospi_d->clock); in stm32_omm_configure()
293 if (clk_enable(omm_d->clock)) in stm32_omm_configure()
302 clk_disable(omm_d->clock); in stm32_omm_configure()
312 if (clk_enable(ospi_d->clock)) in stm32_omm_configure()
H A Dstm32_gpio.c180 struct clk *clock; member
249 if (clk_enable(bank->clock)) in stm32_gpio_get_level()
271 clk_disable(bank->clock); in stm32_gpio_get_level()
283 if (clk_enable(bank->clock)) in stm32_gpio_set_level()
291 clk_disable(bank->clock); in stm32_gpio_set_level()
302 if (clk_enable(bank->clock)) in stm32_gpio_get_direction()
308 clk_disable(bank->clock); in stm32_gpio_get_direction()
335 if (clk_enable(bank->clock)) in stm32_gpio_set_direction()
342 clk_disable(bank->clock); in stm32_gpio_set_direction()
377 if (clk_enable(bank->clock)) in stm32_gpio_configure()
[all …]
/optee_os/core/drivers/firewall/
H A Dstm32_serc.c80 struct clk *clock; member
137 return clk_dt_get_by_index(fdt, node, 0, &pdata->clock); in stm32_serc_parse_fdt()
226 if (clk_enable(serc_dev.pdata.clock)) in probe_serc_device()
251 if (clk_enable(serc_dev.pdata.clock)) in stm32_serc_pm()
255 clk_disable(serc_dev.pdata.clock); in stm32_serc_pm()

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