1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2/* 3 * Copyright (C) 2025, STMicroelectronics - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/clock/st,stm32mp21-rcc.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/firewall/stm32mp21-rifsc.h> 10#include <dt-bindings/firewall/stm32mp25-rif.h> 11#include <dt-bindings/firewall/stm32mp25-risab.h> 12#include <dt-bindings/firewall/stm32mp25-risaf.h> 13#include <dt-bindings/reset/st,stm32mp21-rcc.h> 14 15/ { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a35"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 }; 29 }; 30 31 psci { 32 compatible = "arm,psci-1.0"; 33 method = "smc"; 34 }; 35 36 intc: interrupt-controller@4ac00000 { 37 compatible = "arm,cortex-a7-gic"; 38 #interrupt-cells = <3>; 39 interrupt-controller; 40 reg = <0x0 0x4ac10000 0x0 0x1000>, 41 <0x0 0x4ac20000 0x0 0x2000>, 42 <0x0 0x4ac40000 0x0 0x2000>, 43 <0x0 0x4ac60000 0x0 0x2000>; 44 #address-cells = <1>; 45 }; 46 47 clocks { 48 clk_hse: clk-hse { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <48000000>; 52 }; 53 54 clk_hsi: clk-hsi { 55 #clock-cells = <0>; 56 compatible = "fixed-clock"; 57 clock-frequency = <64000000>; 58 }; 59 60 clk_lse: clk-lse { 61 #clock-cells = <0>; 62 compatible = "fixed-clock"; 63 clock-frequency = <32768>; 64 }; 65 66 clk_lsi: clk-lsi { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <32000>; 70 }; 71 72 clk_msi: clk-msi { 73 #clock-cells = <0>; 74 compatible = "fixed-clock"; 75 clock-frequency = <16000000>; 76 }; 77 78 clk_i2sin: clk-i2sin { 79 #clock-cells = <0>; 80 compatible = "fixed-clock"; 81 clock-frequency = <0>; 82 }; 83 84 clk_rcbsec: clk-rcbsec { 85 #clock-cells = <0>; 86 compatible = "fixed-clock"; 87 clock-frequency = <64000000>; 88 }; 89 }; 90 91 soc@0 { 92 compatible = "simple-bus"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 interrupt-parent = <&intc>; 96 ranges = <0x0 0x0 0x0 0x80000000>; 97 98 rifsc: bus@42080000 { 99 compatible = "st,stm32mp25-rifsc", "simple-bus"; 100 reg = <0x42080000 0x1000>; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 #access-controller-cells = <1>; 104 105 i2c1: i2c@40170000 { 106 compatible = "st,stm32mp25-i2c"; 107 reg = <0x40170000 0x400>; 108 clocks = <&rcc CK_KER_I2C1>; 109 resets = <&rcc I2C1_R>; 110 #address-cells = <1>; 111 #size-cells = <0>; 112 access-controllers = <&rifsc STM32MP21_RIFSC_I2C1_ID>; 113 status = "disabled"; 114 }; 115 116 i2c2: i2c@40180000 { 117 compatible = "st,stm32mp25-i2c"; 118 reg = <0x40180000 0x400>; 119 clocks = <&rcc CK_KER_I2C1>; 120 resets = <&rcc I2C1_R>; 121 #address-cells = <1>; 122 #size-cells = <0>; 123 access-controllers = <&rifsc STM32MP21_RIFSC_I2C2_ID>; 124 status = "disabled"; 125 }; 126 127 iwdg1: watchdog@44010000 { 128 compatible = "st,stm32mp1-iwdg"; 129 reg = <0x44010000 0x400>; 130 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&rcc CK_BUS_IWDG1>, <&rcc LSI_CK>; 132 clock-names = "pclk", "lsi"; 133 access-controllers = <&rifsc STM32MP21_RIFSC_IWDG1_ID>; 134 status = "disabled"; 135 }; 136 137 iwdg2: watchdog@44020000 { 138 compatible = "st,stm32mp1-iwdg"; 139 reg = <0x44020000 0x400>; 140 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&rcc CK_BUS_IWDG2>, <&rcc LSI_CK>; 142 clock-names = "pclk", "lsi"; 143 resets = <&rcc IWDG2_SYS_R>; 144 access-controllers = <&rifsc STM32MP21_RIFSC_IWDG2_ID>; 145 status = "disabled"; 146 }; 147 148 i2c3: i2c@46040000 { 149 compatible = "st,stm32mp25-i2c"; 150 reg = <0x46040000 0x400>; 151 clocks = <&rcc CK_KER_I2C3>; 152 resets = <&rcc I2C3_R>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 access-controllers = <&rifsc STM32MP21_RIFSC_I2C3_ID>; 156 status = "disabled"; 157 }; 158 }; 159 160 iac: iac@42090000 { 161 compatible = "st,stm32mp25-iac"; 162 reg = <0x42090000 0x400>; 163 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 164 }; 165 166 rcc: clock-controller@44200000 { 167 compatible = "st,stm32mp21-rcc", "syscon"; 168 reg = <0x44200000 0x10000>; 169 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 170 171 #clock-cells = <1>; 172 #reset-cells = <1>; 173 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, 174 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>; 175 clock-names = "clk-hse", "clk-hsi", "clk-lse", 176 "clk-lsi", "clk-msi", "clk-i2sin"; 177 }; 178 179 syscfg: syscon@44230000 { 180 reg = <0x44230000 0x10000>; 181 status = "disabled"; 182 }; 183 }; 184}; 185