1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023-2025 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/st,stm32mp25-rcc.h> 8#include <dt-bindings/firewall/stm32mp25-rif.h> 9#include <dt-bindings/firewall/stm32mp25-rifsc.h> 10#include <dt-bindings/firewall/stm32mp25-risaf.h> 11#include <dt-bindings/firewall/stm32mp25-risab.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/st,stm32mp25-rcc.h> 14 15/ { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a35"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 }; 29 }; 30 31 psci { 32 compatible = "arm,psci-1.0"; 33 method = "smc"; 34 }; 35 36 intc: interrupt-controller@4ac00000 { 37 compatible = "arm,cortex-a7-gic"; 38 #interrupt-cells = <3>; 39 interrupt-controller; 40 reg = <0x0 0x4ac10000 0x0 0x1000>, 41 <0x0 0x4ac20000 0x0 0x2000>, 42 <0x0 0x4ac40000 0x0 0x2000>, 43 <0x0 0x4ac60000 0x0 0x2000>; 44 #address-cells = <1>; 45 }; 46 47 clocks { 48 clk_hse: clk-hse { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <24000000>; 52 }; 53 54 clk_hsi: clk-hsi { 55 #clock-cells = <0>; 56 compatible = "fixed-clock"; 57 clock-frequency = <64000000>; 58 }; 59 60 clk_lse: clk-lse { 61 #clock-cells = <0>; 62 compatible = "fixed-clock"; 63 clock-frequency = <32768>; 64 }; 65 66 clk_lsi: clk-lsi { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <32000>; 70 }; 71 72 clk_msi: clk-msi { 73 #clock-cells = <0>; 74 compatible = "fixed-clock"; 75 clock-frequency = <4000000>; 76 }; 77 78 clk_i2sin: clk-i2sin { 79 #clock-cells = <0>; 80 compatible = "fixed-clock"; 81 clock-frequency = <0>; 82 }; 83 84 clk_rcbsec: clk-rcbsec { 85 #clock-cells = <0>; 86 compatible = "fixed-clock"; 87 clock-frequency = <64000000>; 88 }; 89 }; 90 91 soc@0 { 92 compatible = "simple-bus"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 interrupt-parent = <&intc>; 96 ranges = <0x0 0x0 0x0 0x80000000>; 97 98 hpdma1: dma-controller@40400000 { 99 compatible = "st,stm32-dma3"; 100 reg = <0x40400000 0x1000>; 101 clocks = <&rcc CK_BUS_HPDMA1>; 102 resets = <&rcc HPDMA1_R>; 103 #dma-cells = <4>; 104 status = "disabled"; 105 }; 106 107 hpdma2: dma-controller@40410000 { 108 compatible = "st,stm32-dma3"; 109 reg = <0x40410000 0x1000>; 110 clocks = <&rcc CK_BUS_HPDMA2>; 111 resets = <&rcc HPDMA2_R>; 112 #dma-cells = <4>; 113 status = "disabled"; 114 }; 115 116 hpdma3: dma-controller@40420000 { 117 compatible = "st,stm32-dma3"; 118 reg = <0x40420000 0x1000>; 119 clocks = <&rcc CK_BUS_HPDMA3>; 120 resets = <&rcc HPDMA3_R>; 121 #dma-cells = <4>; 122 status = "disabled"; 123 }; 124 125 ipcc1: mailbox@40490000 { 126 compatible = "st,stm32mp25-ipcc"; 127 reg = <0x40490000 0x400>; 128 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 129 interrupt-names = "rx"; 130 clocks = <&rcc CK_BUS_IPCC1>; 131 status = "disabled"; 132 }; 133 134 ommanager: ommanager@40500000 { 135 compatible = "st,stm32mp25-omm"; 136 reg = <0x40500000 0x400>, <0x60000000 0x10000000>; 137 reg-names = "regs", "memory_map"; 138 ranges = <0 0 0x40430000 0x400>, 139 <1 0 0x40440000 0x400>; 140 clocks = <&rcc CK_BUS_OSPIIOM>; 141 resets = <&rcc OSPIIOM_R>; 142 #address-cells = <2>; 143 #size-cells = <1>; 144 st,syscfg-amcr = <&syscfg 0x2c00 0x7>; 145 status = "disabled"; 146 147 ospi1: spi@0 { 148 compatible = "st,stm32mp25-ospi"; 149 reg = <0 0 0x400>; 150 clocks = <&rcc CK_KER_OSPI1>; 151 resets = <&rcc OSPI1_R>, <&rcc OSPI1DLL_R>; 152 status = "disabled"; 153 }; 154 155 ospi2: spi@1 { 156 compatible = "st,stm32mp25-ospi"; 157 reg = <1 0 0x400>; 158 clocks = <&rcc CK_KER_OSPI2>; 159 resets = <&rcc OSPI2_R>, <&rcc OSPI2DLL_R>; 160 status = "disabled"; 161 }; 162 }; 163 164 rifsc: rifsc@42080000 { 165 compatible = "st,stm32mp25-rifsc", "simple-bus"; 166 reg = <0x42080000 0x1000>; 167 #address-cells = <1>; 168 #size-cells = <1>; 169 #access-controller-cells = <1>; 170 171 usart2: serial@400e0000 { 172 compatible = "st,stm32h7-uart"; 173 reg = <0x400e0000 0x400>; 174 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&rcc CK_KER_USART2>; 176 access-controllers = <&rifsc STM32MP25_RIFSC_USART2_ID>; 177 status = "disabled"; 178 }; 179 180 i2c1: i2c@40120000 { 181 compatible = "st,stm32mp25-i2c"; 182 reg = <0x40120000 0x400>; 183 clocks = <&rcc CK_KER_I2C1>; 184 resets = <&rcc I2C1_R>; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 access-controllers = <&rifsc STM32MP25_RIFSC_I2C1_ID>; 188 status = "disabled"; 189 }; 190 191 i2c2: i2c@40130000 { 192 compatible = "st,stm32mp25-i2c"; 193 reg = <0x40130000 0x400>; 194 clocks = <&rcc CK_KER_I2C2>; 195 resets = <&rcc I2C2_R>; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 access-controllers = <&rifsc STM32MP25_RIFSC_I2C2_ID>; 199 status = "disabled"; 200 }; 201 202 i2c3: i2c@40140000 { 203 compatible = "st,stm32mp25-i2c"; 204 reg = <0x40140000 0x400>; 205 clocks = <&rcc CK_KER_I2C3>; 206 resets = <&rcc I2C3_R>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 access-controllers = <&rifsc STM32MP25_RIFSC_I2C3_ID>; 210 status = "disabled"; 211 }; 212 213 i2c4: i2c@40150000 { 214 compatible = "st,stm32mp25-i2c"; 215 reg = <0x40150000 0x400>; 216 clocks = <&rcc CK_KER_I2C4>; 217 resets = <&rcc I2C4_R>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 access-controllers = <&rifsc STM32MP25_RIFSC_I2C4_ID>; 221 status = "disabled"; 222 }; 223 224 i2c5: i2c@40160000 { 225 compatible = "st,stm32mp25-i2c"; 226 reg = <0x40160000 0x400>; 227 clocks = <&rcc CK_KER_I2C5>; 228 resets = <&rcc I2C5_R>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 access-controllers = <&rifsc STM32MP25_RIFSC_I2C5_ID>; 232 status = "disabled"; 233 }; 234 235 i2c6: i2c@40170000 { 236 compatible = "st,stm32mp25-i2c"; 237 reg = <0x40170000 0x400>; 238 clocks = <&rcc CK_KER_I2C6>; 239 resets = <&rcc I2C6_R>; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 access-controllers = <&rifsc STM32MP25_RIFSC_I2C6_ID>; 243 status = "disabled"; 244 }; 245 246 i2c7: i2c@40180000 { 247 compatible = "st,stm32mp25-i2c"; 248 reg = <0x40180000 0x400>; 249 clocks = <&rcc CK_KER_I2C7>; 250 resets = <&rcc I2C7_R>; 251 #address-cells = <1>; 252 #size-cells = <0>; 253 access-controllers = <&rifsc STM32MP25_RIFSC_I2C7_ID>; 254 status = "disabled"; 255 }; 256 257 rng: rng@42020000 { 258 compatible = "st,stm32mp25-rng"; 259 reg = <0x42020000 0x400>; 260 clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; 261 clock-names = "rng_clk", "rng_hclk"; 262 resets = <&rcc RNG_R>; 263 access-controllers = <&rifsc STM32MP25_RIFSC_RNG_ID>; 264 }; 265 266 iwdg1: watchdog@44010000 { 267 compatible = "st,stm32mp1-iwdg"; 268 reg = <0x44010000 0x400>; 269 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&rcc CK_BUS_IWDG1>, <&rcc LSI_CK>; 271 clock-names = "pclk", "lsi"; 272 access-controllers = <&rifsc STM32MP25_RIFSC_IWDG1_ID>; 273 status = "disabled"; 274 }; 275 276 iwdg2: watchdog@44020000 { 277 compatible = "st,stm32mp1-iwdg"; 278 reg = <0x44020000 0x400>; 279 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 280 clocks = <&rcc CK_BUS_IWDG2>, <&rcc LSI_CK>; 281 clock-names = "pclk", "lsi"; 282 resets = <&rcc IWDG2_SYS_R>; 283 access-controllers = <&rifsc STM32MP25_RIFSC_IWDG2_ID>; 284 status = "disabled"; 285 }; 286 287 i2c8: i2c@46040000 { 288 compatible = "st,stm32mp25-i2c"; 289 reg = <0x46040000 0x400>; 290 clocks = <&rcc CK_KER_I2C8>; 291 resets = <&rcc I2C8_R>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 access-controllers = <&rifsc STM32MP25_RIFSC_I2C8_ID>; 295 status = "disabled"; 296 }; 297 }; 298 299 iac: iac@42090000 { 300 compatible = "st,stm32mp25-iac"; 301 reg = <0x42090000 0x400>; 302 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 303 }; 304 305 risaf1: risaf@420a0000 { 306 compatible = "st,stm32mp25-risaf"; 307 reg = <0x420a0000 0x1000>; 308 clocks = <&rcc CK_BUS_BKPSRAM>; 309 st,mem-map = <0x0 0x42000000 0x0 0x2000>; 310 #access-controller-cells = <1>; 311 }; 312 313 risaf2: risaf@420b0000 { 314 compatible = "st,stm32mp25-risaf"; 315 reg = <0x420b0000 0x1000>; 316 clocks = <&rcc CK_KER_OSPI1>; 317 st,mem-map = <0x0 0x60000000 0x0 0x10000000>; 318 #access-controller-cells = <1>; 319 status = "disabled"; 320 }; 321 322 risaf4: risaf@420d0000 { 323 compatible = "st,stm32mp25-risaf-enc"; 324 reg = <0x420d0000 0x1000>; 325 clocks = <&rcc CK_BUS_RISAF4>; 326 st,mem-map = <0x0 0x80000000 0x1 0x00000000>; 327 #access-controller-cells = <1>; 328 }; 329 330 risaf5: risaf@420e0000 { 331 compatible = "st,stm32mp25-risaf"; 332 reg = <0x420e0000 0x1000>; 333 clocks = <&rcc CK_BUS_PCIE>; 334 st,mem-map = <0x0 0x10000000 0x0 0x10000000>; 335 #access-controller-cells = <1>; 336 status = "disabled"; 337 }; 338 339 risab1: risab@420f0000 { 340 compatible = "st,stm32mp25-risab"; 341 reg = <0x420f0000 0x1000>; 342 clocks = <&rcc CK_ICN_LS_MCU>; 343 st,mem-map = <0xa000000 0x20000>; 344 #access-controller-cells = <1>; 345 }; 346 347 risab2: risab@42100000 { 348 compatible = "st,stm32mp25-risab"; 349 reg = <0x42100000 0x1000>; 350 clocks = <&rcc CK_ICN_LS_MCU>; 351 st,mem-map = <0xa020000 0x20000>; 352 #access-controller-cells = <1>; 353 }; 354 355 risab3: risab@42110000 { 356 compatible = "st,stm32mp25-risab"; 357 reg = <0x42110000 0x1000>; 358 clocks = <&rcc CK_ICN_LS_MCU>; 359 st,mem-map = <0xa040000 0x20000>; 360 #access-controller-cells = <1>; 361 }; 362 363 risab4: risab@42120000 { 364 compatible = "st,stm32mp25-risab"; 365 reg = <0x42120000 0x1000>; 366 clocks = <&rcc CK_ICN_LS_MCU>; 367 st,mem-map = <0xa060000 0x20000>; 368 #access-controller-cells = <1>; 369 }; 370 371 risab5: risab@42130000 { 372 compatible = "st,stm32mp25-risab"; 373 reg = <0x42130000 0x1000>; 374 clocks = <&rcc CK_ICN_LS_MCU>; 375 st,mem-map = <0xa080000 0x20000>; 376 #access-controller-cells = <1>; 377 }; 378 379 risab6: risab@42140000 { 380 compatible = "st,stm32mp25-risab"; 381 reg = <0x42140000 0x1000>; 382 clocks = <&rcc CK_ICN_LS_MCU>; 383 st,mem-map = <0xa0a0000 0x20000>; 384 #access-controller-cells = <1>; 385 status = "disabled"; 386 }; 387 388 serc: serc@44080000 { 389 compatible = "st,stm32mp25-serc"; 390 reg = <0x44080000 0x1000>; 391 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&rcc CK_BUS_SERC>; 393 }; 394 395 rcc: rcc@44200000 { 396 compatible = "st,stm32mp25-rcc", "syscon"; 397 reg = <0x44200000 0x10000>; 398 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 399 400 #clock-cells = <1>; 401 #reset-cells = <1>; 402 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, 403 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>; 404 clock-names = "clk-hse", "clk-hsi", "clk-lse", 405 "clk-lsi", "clk-msi", "clk-i2sin"; 406 407 hsi_calibration: hsi-calibration { 408 compatible = "st,hsi-cal"; 409 st,cal_hsi_dev = <31>; 410 st,cal_hsi_ref = <1953>; 411 status = "disabled"; 412 }; 413 414 msi_calibration: msi-calibration { 415 compatible = "st,msi-cal"; 416 status = "disabled"; 417 }; 418 }; 419 420 exti1: interrupt-controller@44220000 { 421 compatible = "st,stm32mp1-exti"; 422 interrupt-controller; 423 #interrupt-cells = <2>; 424 reg = <0x44220000 0x400>; 425 interrupts-extended = 426 <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 427 <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 428 <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 429 <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 430 <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 431 <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 432 <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 433 <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 434 <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 435 <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 436 <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 437 <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 438 <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 439 <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 440 <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 441 <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 442 <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 443 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 444 <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 445 <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 446 <0>, /* EXTI_20 */ 447 <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 448 <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 449 <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 450 <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 451 <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 452 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 453 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 454 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 455 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 456 <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 457 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 458 <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 459 <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 460 <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 461 <0>, 462 <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 463 <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 464 <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 465 <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 466 <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 467 <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 468 <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 469 <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 470 <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 471 <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 472 <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 473 <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 474 <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 475 <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 476 <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 477 <0>, 478 <0>, 479 <0>, 480 <0>, 481 <0>, 482 <0>, 483 <0>, 484 <0>, 485 <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 486 <0>, /* EXTI_60 */ 487 <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 488 <0>, 489 <0>, 490 <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 491 <0>, 492 <0>, 493 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 494 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 495 <0>, 496 <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 497 <0>, 498 <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 499 <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 500 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 501 <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 502 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 503 <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 504 <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 505 <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 506 <0>, /* EXTI_80 */ 507 <0>, 508 <0>, 509 <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 510 <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 511 }; 512 513 syscfg: syscon@44230000 { 514 reg = <0x44230000 0x10000>; 515 status = "disabled"; 516 }; 517 518 pinctrl: pinctrl@44240000 { 519 #address-cells = <1>; 520 #size-cells = <1>; 521 compatible = "st,stm32mp257-pinctrl"; 522 ranges = <0 0x44240000 0xa0400>; 523 524 gpioa: gpio@44240000 { 525 gpio-controller; 526 #gpio-cells = <2>; 527 interrupt-controller; 528 #interrupt-cells = <2>; 529 #access-controller-cells = <1>; 530 reg = <0x0 0x400>; 531 clocks = <&rcc CK_BUS_GPIOA>; 532 st,bank-name = "GPIOA"; 533 status = "disabled"; 534 }; 535 536 gpiob: gpio@44250000 { 537 gpio-controller; 538 #gpio-cells = <2>; 539 interrupt-controller; 540 #interrupt-cells = <2>; 541 #access-controller-cells = <1>; 542 reg = <0x10000 0x400>; 543 clocks = <&rcc CK_BUS_GPIOB>; 544 st,bank-name = "GPIOB"; 545 status = "disabled"; 546 }; 547 548 gpioc: gpio@44260000 { 549 gpio-controller; 550 #gpio-cells = <2>; 551 interrupt-controller; 552 #interrupt-cells = <2>; 553 #access-controller-cells = <1>; 554 reg = <0x20000 0x400>; 555 clocks = <&rcc CK_BUS_GPIOC>; 556 st,bank-name = "GPIOC"; 557 status = "disabled"; 558 }; 559 560 gpiod: gpio@44270000 { 561 gpio-controller; 562 #gpio-cells = <2>; 563 interrupt-controller; 564 #interrupt-cells = <2>; 565 #access-controller-cells = <1>; 566 reg = <0x30000 0x400>; 567 clocks = <&rcc CK_BUS_GPIOD>; 568 st,bank-name = "GPIOD"; 569 status = "disabled"; 570 }; 571 572 gpioe: gpio@44280000 { 573 gpio-controller; 574 #gpio-cells = <2>; 575 interrupt-controller; 576 #interrupt-cells = <2>; 577 #access-controller-cells = <1>; 578 reg = <0x40000 0x400>; 579 clocks = <&rcc CK_BUS_GPIOE>; 580 st,bank-name = "GPIOE"; 581 status = "disabled"; 582 }; 583 584 gpiof: gpio@44290000 { 585 gpio-controller; 586 #gpio-cells = <2>; 587 interrupt-controller; 588 #interrupt-cells = <2>; 589 #access-controller-cells = <1>; 590 reg = <0x50000 0x400>; 591 clocks = <&rcc CK_BUS_GPIOF>; 592 st,bank-name = "GPIOF"; 593 status = "disabled"; 594 }; 595 596 gpiog: gpio@442a0000 { 597 gpio-controller; 598 #gpio-cells = <2>; 599 interrupt-controller; 600 #interrupt-cells = <2>; 601 #access-controller-cells = <1>; 602 reg = <0x60000 0x400>; 603 clocks = <&rcc CK_BUS_GPIOG>; 604 st,bank-name = "GPIOG"; 605 status = "disabled"; 606 }; 607 608 gpioh: gpio@442b0000 { 609 gpio-controller; 610 #gpio-cells = <2>; 611 interrupt-controller; 612 #interrupt-cells = <2>; 613 #access-controller-cells = <1>; 614 reg = <0x70000 0x400>; 615 clocks = <&rcc CK_BUS_GPIOH>; 616 st,bank-name = "GPIOH"; 617 status = "disabled"; 618 }; 619 620 gpioi: gpio@442c0000 { 621 gpio-controller; 622 #gpio-cells = <2>; 623 interrupt-controller; 624 #interrupt-cells = <2>; 625 #access-controller-cells = <1>; 626 reg = <0x80000 0x400>; 627 clocks = <&rcc CK_BUS_GPIOI>; 628 st,bank-name = "GPIOI"; 629 status = "disabled"; 630 }; 631 632 gpioj: gpio@442d0000 { 633 gpio-controller; 634 #gpio-cells = <2>; 635 interrupt-controller; 636 #interrupt-cells = <2>; 637 #access-controller-cells = <1>; 638 reg = <0x90000 0x400>; 639 clocks = <&rcc CK_BUS_GPIOJ>; 640 st,bank-name = "GPIOJ"; 641 status = "disabled"; 642 }; 643 644 gpiok: gpio@442e0000 { 645 gpio-controller; 646 #gpio-cells = <2>; 647 interrupt-controller; 648 #interrupt-cells = <2>; 649 #access-controller-cells = <1>; 650 reg = <0xa0000 0x400>; 651 clocks = <&rcc CK_BUS_GPIOK>; 652 st,bank-name = "GPIOK"; 653 status = "disabled"; 654 }; 655 }; 656 657 rtc: rtc@46000000 { 658 compatible = "st,stm32mp25-rtc"; 659 reg = <0x46000000 0x400>; 660 clocks = <&rcc CK_BUS_RTC>, <&rcc RTC_CK>; 661 clock-names = "pclk", "rtc_ck"; 662 wakeup-source; 663 interrupts-extended = <&exti2 22 IRQ_TYPE_EDGE_RISING>; 664 }; 665 666 tamp: tamp@46010000 { 667 compatible = "st,stm32mp25-tamp"; 668 reg = <0x46010000 0x400>; 669 clocks = <&rcc CK_BUS_RTC>; 670 interrupts-extended = <&exti2 21 IRQ_TYPE_EDGE_RISING>; 671 #address-cells = <1>; 672 #size-cells = <1>; 673 ranges; 674 st,backup-zones = <24 24 24 24 12 12 8>; 675 }; 676 677 pinctrl_z: pinctrl-z@46200000 { 678 #address-cells = <1>; 679 #size-cells = <1>; 680 compatible = "st,stm32mp257-z-pinctrl"; 681 ranges = <0 0x46200000 0x400>; 682 683 gpioz: gpio@46200000 { 684 gpio-controller; 685 #gpio-cells = <2>; 686 interrupt-controller; 687 #interrupt-cells = <2>; 688 #access-controller-cells = <1>; 689 reg = <0 0x400>; 690 clocks = <&rcc CK_BUS_GPIOZ>; 691 st,bank-name = "GPIOZ"; 692 st,bank-ioport = <11>; 693 status = "disabled"; 694 }; 695 }; 696 697 exti2: interrupt-controller@46230000 { 698 compatible = "st,stm32mp1-exti"; 699 interrupt-controller; 700 #interrupt-cells = <2>; 701 reg = <0x46230000 0x400>; 702 interrupts-extended = 703 <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 704 <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 705 <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 706 <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 707 <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 708 <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 709 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 710 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 711 <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 712 <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 713 <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 714 <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 715 <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 716 <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 717 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 718 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 719 <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 720 <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 721 <0>, 722 <0>, 723 <0>, /* EXTI_20 */ 724 <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 725 <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 726 <0>, 727 <0>, 728 <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 729 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 730 <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 731 <0>, 732 <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 733 <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 734 <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 735 <0>, 736 <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 737 <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 738 <0>, 739 <0>, 740 <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 741 <0>, 742 <0>, 743 <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 744 <0>, 745 <0>, 746 <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 747 <0>, 748 <0>, 749 <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 750 <0>, 751 <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 752 <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 753 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 754 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 755 <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 756 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 757 <0>, 758 <0>, 759 <0>, 760 <0>, 761 <0>, 762 <0>, 763 <0>, /* EXTI_60 */ 764 <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 765 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 766 <0>, 767 <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 768 <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 769 <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 770 <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 771 <0>, 772 <0>, 773 <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 774 }; 775 776 hsem: hwspinlock@46240000 { 777 compatible = "st,stm32mp25-hsem"; 778 reg = <0x46240000 0x400>; 779 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&rcc CK_BUS_HSEM>; 781 status = "disabled"; 782 }; 783 784 ipcc2: mailbox@46250000 { 785 compatible = "st,stm32mp25-ipcc"; 786 reg = <0x46250000 0x400>; 787 clocks = <&rcc CK_BUS_IPCC2>; 788 status = "disabled"; 789 }; 790 791 stgenc: stgen@48080000 { 792 compatible = "st,stm32mp25-stgen"; 793 reg = <0x48080000 0x1000>; 794 clocks = <&rcc CK_BUS_STGEN>, <&rcc CK_KER_STGEN>; 795 clock-names = "bus", "stgen_clk"; 796 }; 797 798 fmc: memory-controller@48200000 { 799 compatible = "st,stm32mp25-fmc2-ebi"; 800 reg = <0x48200000 0x400>; 801 ranges = <0 0 0x70000000 0x04000000>, /* EBI CS 1 */ 802 <1 0 0x74000000 0x04000000>, /* EBI CS 2 */ 803 <2 0 0x78000000 0x04000000>, /* EBI CS 3 */ 804 <3 0 0x7c000000 0x04000000>, /* EBI CS 4 */ 805 <4 0 0x48810000 0x00001000>; /* NAND */ 806 #address-cells = <2>; 807 #size-cells = <1>; 808 clocks = <&rcc CK_KER_FMC>; 809 resets = <&rcc FMC_R>; 810 status = "disabled"; 811 }; 812 }; 813}; 814