dts: stm32: default enable RTC on stm32mp1

TAMP peripheral has a dependency on RTC.
Since TAMP is enable by default in stm32mp131.dtsi and stm32mp151.dtsi.
Default probe RTC to solve TAMP's dependen

dts: stm32: default enable RTC on stm32mp1

TAMP peripheral has a dependency on RTC.
Since TAMP is enable by default in stm32mp131.dtsi and stm32mp151.dtsi.
Default probe RTC to solve TAMP's dependency on it.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add missing i2c1 and i2c2 instances in stm32mp131.dtsi

i2c1 and i2c2 instances were missing within the stm32mp131.dtsi file
hence add them to have complete description of the stm32mp131

dts: stm32: add missing i2c1 and i2c2 instances in stm32mp131.dtsi

i2c1 and i2c2 instances were missing within the stm32mp131.dtsi file
hence add them to have complete description of the stm32mp131 i2c
controllers.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: stm32mp1_pwr: fix compatible

Remove the unexpected comma in compatible name "st,stm32mp1,pwr-reg"

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Thomas

plat-stm32mp1: stm32mp1_pwr: fix compatible

Remove the unexpected comma in compatible name "st,stm32mp1,pwr-reg"

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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treewide: dts: stm32: remove deprecated pins-are-numbered in device tree

Align the binding and the stm32mp device tree with Linux kernel,
remove the deprecated properties pins-are-numbered.

No func

treewide: dts: stm32: remove deprecated pins-are-numbered in device tree

Align the binding and the stm32mp device tree with Linux kernel,
remove the deprecated properties pins-are-numbered.

No functional impact as it is not used in code.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: use EXTI event instead of GIC SPI for TAMP in stm32mp131.dtsi

Rely on EXTI event for the tamper event detection instead of the GIC line.
The EXTI makes the link with the GIC and provides

dts: stm32: use EXTI event instead of GIC SPI for TAMP in stm32mp131.dtsi

Rely on EXTI event for the tamper event detection instead of the GIC line.
The EXTI makes the link with the GIC and provides wakeup capabilities.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add EXTI node in stm32mp131

Add the EXTI support for stm32mp13 SoC.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

dts: stm32: describe supported-hw on CPU OPP for STM32MP13

Describe supported hardware for each OPP.

Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Acked-by: Etienne Carriere <etienne.carrie

dts: stm32: describe supported-hw on CPU OPP for STM32MP13

Describe supported hardware for each OPP.

Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: describe CPU OPP for STM32MP13

Describe CPU operating points for STM32MP13 boards.

Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@fos

dts: stm32: describe CPU OPP for STM32MP13

Describe CPU operating points for STM32MP13 boards.

Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>

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dts: stm32: define SoC GPIO banks that are firewall controllers

Add property #access-controller-cells to GPIO banks that register
to the firewall framework.

Signed-off-by: Etienne Carriere <etienne

dts: stm32: define SoC GPIO banks that are firewall controllers

Add property #access-controller-cells to GPIO banks that register
to the firewall framework.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: add st,backup-zones property in TAMP node in stm32mp131.dtsi

Add st,backup-zones property in TAMP node in stm32mp131.dtsi.
It defines the topology of the backup registers zones. The numb

dts: stm32: add st,backup-zones property in TAMP node in stm32mp131.dtsi

Add st,backup-zones property in TAMP node in stm32mp131.dtsi.
It defines the topology of the backup registers zones. The number of zones
on stm32mp13x platforms is 3.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: define ETZPC as an access controller for stm32mp13 platforms

ETZPC is a firewall controller. Add the access-controllers property to
all ETZPC sub-nodes on stm32mp13 platforms. Also add t

dts: stm32: define ETZPC as an access controller for stm32mp13 platforms

ETZPC is a firewall controller. Add the access-controllers property to
all ETZPC sub-nodes on stm32mp13 platforms. Also add the "simple-bus"
compatible for backward compatibility and "#access-controllers-cells"
to the ETZPC node.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add the ETZPC configuration table for stm32mp1x boards

Add the tables defining the ETZPC firewall controller configuration
that will be set at boot time on stm32mp1x boards.

Signed-off-

dts: stm32: add the ETZPC configuration table for stm32mp1x boards

Add the tables defining the ETZPC firewall controller configuration
that will be set at boot time on stm32mp1x boards.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Johann Neuhauser <jneuhauser@dh-electronics.com>

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dts: stm32mp13: IO domain regulators

Define STM32MP13 IO domains regulators of the stm32mp13f-dk board
based on recently merge stm32mp1_regulator_io driver.

Acked-by: Patrick Delaunay <patrick.dela

dts: stm32mp13: IO domain regulators

Define STM32MP13 IO domains regulators of the stm32mp13f-dk board
based on recently merge stm32mp1_regulator_io driver.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32mp13: update stm32mp13 SoC and board DTS files

Updates STM32MP13* SoC DTSI files and STM32MP135F-DK board DTS file
and related DT binding header files.

Acked-by: Gatien Chevallier <gatien

dts: stm32mp13: update stm32mp13 SoC and board DTS files

Updates STM32MP13* SoC DTSI files and STM32MP135F-DK board DTS file
and related DT binding header files.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: enable hardware rng for STM32MP13

Adds RNG node in stm32mp131.dtsi and enables it in stm32mp135f-dk.dts.

Default disables CFG_WITH_SOFTWARE_PRNG for STM32MP13: OP-TEE uses
the HW RNG

plat-stm32mp1: enable hardware rng for STM32MP13

Adds RNG node in stm32mp131.dtsi and enables it in stm32mp135f-dk.dts.

Default disables CFG_WITH_SOFTWARE_PRNG for STM32MP13: OP-TEE uses
the HW RNG support.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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dts: stm32: correct BSEC nodes compatible for stm32mp13

Device tree alignment with kernel and latest binding for BSEC node:
the rev2.0 is used on STM32MP13x devices with the new compatible
compatibl

dts: stm32: correct BSEC nodes compatible for stm32mp13

Device tree alignment with kernel and latest binding for BSEC node:
the rev2.0 is used on STM32MP13x devices with the new compatible
compatible = "st,stm32mp13-bsec".

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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dts: stm32: add nvmem layout

Add the nvmem layout for each BSEC associated fuses, update the SOC and
ST boards device trees with OTP cells node.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.s

dts: stm32: add nvmem layout

Add the nvmem layout for each BSEC associated fuses, update the SOC and
ST boards device trees with OTP cells node.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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dts: stm32: add STM32MP13 SoCs support

Add initial support of STM32MP13 family. The STM32MP13 SoC diversity is
composed by:
- STM32MP131:
-core: 1*CA7, 17*TIMERS, 5*LPTIMERS, DMA/MDMA/DMAMUX
-st

dts: stm32: add STM32MP13 SoCs support

Add initial support of STM32MP13 family. The STM32MP13 SoC diversity is
composed by:
- STM32MP131:
-core: 1*CA7, 17*TIMERS, 5*LPTIMERS, DMA/MDMA/DMAMUX
-storage: 3*SDMCC, 1*QSPI, FMC
-com: USB (OHCI/EHCI, OTG), 5*I2C, 5*SPI/I2S, 8*U(S)ART
-audio: 2*SAI
-network: 1*ETH(GMAC)
-STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1
-STM32MP135: STM32MP133 + DCMIPP, LTDC

Co-developed-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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