xref: /optee_os/core/arch/arm/dts/stm32mp211.dtsi (revision 720ffc4a24e8d4449c868a35835523468639a2a9)

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
 * Copyright (C) 2025, STMicroelectronics - All Rights Reserved
 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
 */
#include <dt-bindings/clock/st,stm32mp21-rcc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/firewall/stm32mp21-rifsc.h>
#include <dt-bindings/firewall/stm32mp25-rif.h>
#include <dt-bindings/firewall/stm32mp25-risab.h>
#include <dt-bindings/firewall/stm32mp25-risaf.h>
#include <dt-bindings/reset/st,stm32mp21-rcc.h>

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a35";
			device_type = "cpu";
			reg = <0>;
			enable-method = "psci";
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	intc: interrupt-controller@4ac00000 {
		compatible = "arm,cortex-a7-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x4ac10000 0x0 0x1000>,
		      <0x0 0x4ac20000 0x0 0x2000>,
		      <0x0 0x4ac40000 0x0 0x2000>,
		      <0x0 0x4ac60000 0x0 0x2000>;
		#address-cells = <1>;
	};

	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <48000000>;
		};

		clk_hsi: clk-hsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <64000000>;
		};

		clk_lse: clk-lse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		clk_lsi: clk-lsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32000>;
		};

		clk_msi: clk-msi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <16000000>;
		};

		clk_i2sin: clk-i2sin {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};

		clk_rcbsec: clk-rcbsec {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <64000000>;
		};
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges = <0x0 0x0 0x0 0x80000000>;

		rifsc: bus@42080000 {
			compatible = "st,stm32mp25-rifsc", "simple-bus";
			reg = <0x42080000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			#access-controller-cells = <1>;

			i2c1: i2c@40170000 {
				compatible = "st,stm32mp25-i2c";
				reg = <0x40170000 0x400>;
				clocks = <&rcc CK_KER_I2C1>;
				resets = <&rcc I2C1_R>;
				#address-cells = <1>;
				#size-cells = <0>;
				access-controllers = <&rifsc STM32MP21_RIFSC_I2C1_ID>;
				status = "disabled";
			};

			i2c2: i2c@40180000 {
				compatible = "st,stm32mp25-i2c";
				reg = <0x40180000 0x400>;
				clocks = <&rcc CK_KER_I2C1>;
				resets = <&rcc I2C1_R>;
				#address-cells = <1>;
				#size-cells = <0>;
				access-controllers = <&rifsc STM32MP21_RIFSC_I2C2_ID>;
				status = "disabled";
			};

			iwdg1: watchdog@44010000 {
				compatible = "st,stm32mp1-iwdg";
				reg = <0x44010000 0x400>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_BUS_IWDG1>, <&rcc LSI_CK>;
				clock-names = "pclk", "lsi";
				access-controllers = <&rifsc STM32MP21_RIFSC_IWDG1_ID>;
				status = "disabled";
			};

			iwdg2: watchdog@44020000 {
				compatible = "st,stm32mp1-iwdg";
				reg = <0x44020000 0x400>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&rcc CK_BUS_IWDG2>, <&rcc LSI_CK>;
				clock-names = "pclk", "lsi";
				resets = <&rcc IWDG2_SYS_R>;
				access-controllers = <&rifsc STM32MP21_RIFSC_IWDG2_ID>;
				status = "disabled";
			};

			i2c3: i2c@46040000 {
				compatible = "st,stm32mp25-i2c";
				reg = <0x46040000 0x400>;
				clocks = <&rcc CK_KER_I2C3>;
				resets = <&rcc I2C3_R>;
				#address-cells = <1>;
				#size-cells = <0>;
				access-controllers = <&rifsc STM32MP21_RIFSC_I2C3_ID>;
				status = "disabled";
			};
		};

		iac: iac@42090000 {
			compatible = "st,stm32mp25-iac";
			reg = <0x42090000 0x400>;
			interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
		};

		rcc: clock-controller@44200000 {
			compatible = "st,stm32mp21-rcc", "syscon";
			reg = <0x44200000 0x10000>;
			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;

			#clock-cells = <1>;
			#reset-cells = <1>;
			clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>,
				 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>;
			clock-names = "clk-hse", "clk-hsi", "clk-lse",
				      "clk-lsi", "clk-msi", "clk-i2sin";
		};

		syscfg: syscon@44230000 {
			reg = <0x44230000 0x10000>;
			status = "disabled";
		};
	};
};