arm/dts/sama7g5.dtsi

11 #include <dt-bindings/clock/at91.h>
34 			clock-names = "cpu";
46 			clock-latency-ns = <320000>;
52 			clock-latency-ns = <320000>;
58 			clock-latency-ns = <320000>;
65 			clock-latency-ns = <320000>;
71 			clock-latency-ns = <320000>;
115 			compatible = "fixed-clock";
116 			#clock-cells = <0>;
120 			compatible = "fixed-clock";
121 			#clock-cells = <0>;
125 			compatible = "fixed-clock";
126 			#clock-cells = <0>;
127 			clock-frequency = <48000000>;
134 		#clock-cells = <1>;
136 		clock-names = "utmi_clk";
150 			clock-names = "utmi_clk";
159 			clock-names = "utmi_clk";
168 			clock-names = "utmi_clk";
215 			clock-names = "pclk", "hclk";
227 			clock-names = "pclk", "hclk";
235 			clock-names = "ohci_clk", "hclk", "uhpck";
244 			clock-names = "usb_clk", "ehci_clk";
334 			#clock-cells = <2>;
336 			clock-names = "td_slck", "md_slck", "main_xtal";
369 		clk32k: clock-controller@e001d050 {
373 			#clock-cells = <1>;
413 			clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
443 			clock-names = "pclk", "gclk";
445 			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
446 			assigned-clock-rates = <133000000>;
461 			clock-names = "pclk", "gclk";
475 			clock-names = "hclk", "cclk";
477 			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
478 			assigned-clock-rates = <40000000>;
491 			clock-names = "hclk", "cclk";
493 			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
494 			assigned-clock-rates = <40000000>;
507 			clock-names = "hclk", "cclk";
509 			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
510 			assigned-clock-rates = <40000000>;
523 			clock-names = "hclk", "cclk";
525 			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
526 			assigned-clock-rates = <40000000>;
539 			clock-names = "hclk", "cclk";
541 			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
542 			assigned-clock-rates = <40000000>;
555 			clock-names = "hclk", "cclk";
557 			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
558 			assigned-clock-rates = <40000000>;
569 			assigned-clock-rates = <100000000>;
570 			clock-names = "adc_clk";
587 			clock-names = "hclock", "multclk";
588 			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
590 			assigned-clock-rates = <200000000>;
600 			clock-names = "hclock", "multclk";
601 			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
603 			assigned-clock-rates = <200000000>;
613 			clock-names = "hclock", "multclk";
614 			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
616 			assigned-clock-rates = <200000000>;
628 			clock-names = "perclk", "phyclk";
630 			assigned-clock-rates = <26600000>;
662 			clock-names = "pclk", "scck";
664 			assigned-clock-rates = <266000000>;
693 			clock-names = "hclock";
694 			#clock-cells = <0>;
695 			clock-output-names = "isc-mck";
726 			clock-names = "pclk", "gclk";
739 			clock-names = "pclk", "gclk";
760 			clock-names = "pclk", "gclk";
765 			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_AUDIOPMCPLL>;
777 			clock-names = "pclk", "gclk";
790 			clock-names = "pclk", "gclk";
802 			clock-names = "pclk", "gclk";
815 			clock-names = "pclk", "gclk";
834 			clock-names = "pclk";
843 			clock-names = "pclk", "gclk";
851 			clock-names = "pclk", "gclk";
863 			clock-names = "pclk";
873 			clock-names = "aes_clk";
885 			clock-names = "sha_clk";
905 				clock-names = "usart";
953 				clock-names = "usart";
972 			clock-names = "pclk";
991 			clock-names = "tdes_clk";
1012 				clock-names = "usart";
1037 				clock-names = "usart";
1058 			clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
1060 			assigned-clock-rates = <125000000>;
1061 			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_ETHPLL>;
1071 			clock-names = "pclk", "hclk", "tsu_clk";
1073 			assigned-clock-rates = <200000000>;
1083 			clock-names = "dma_clk";
1093 			clock-names = "dma_clk";
1104 			clock-names = "dma_clk";
1116 			clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
1181 				clock-names = "spi_clk";