1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2/* 3 * Copyright (C) 2025, STMicroelectronics - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/st,stm32mp25-rcc.h> 8#include <dt-bindings/firewall/stm32mp25-rif.h> 9#include <dt-bindings/firewall/stm32mp25-rifsc.h> 10#include <dt-bindings/firewall/stm32mp25-risab.h> 11#include <dt-bindings/firewall/stm32mp25-risaf.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/st,stm32mp25-rcc.h> 14 15/ { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a35"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 }; 29 }; 30 31 psci { 32 compatible = "arm,psci-1.0"; 33 method = "smc"; 34 }; 35 36 intc: interrupt-controller@4ac00000 { 37 compatible = "arm,cortex-a7-gic"; 38 #interrupt-cells = <3>; 39 interrupt-controller; 40 reg = <0x0 0x4ac10000 0x0 0x1000>, 41 <0x0 0x4ac20000 0x0 0x2000>, 42 <0x0 0x4ac40000 0x0 0x2000>, 43 <0x0 0x4ac60000 0x0 0x2000>; 44 #address-cells = <1>; 45 }; 46 47 clocks { 48 clk_hse: clk-hse { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <24000000>; 52 }; 53 54 clk_hsi: clk-hsi { 55 #clock-cells = <0>; 56 compatible = "fixed-clock"; 57 clock-frequency = <64000000>; 58 }; 59 60 clk_lse: clk-lse { 61 #clock-cells = <0>; 62 compatible = "fixed-clock"; 63 clock-frequency = <32768>; 64 }; 65 66 clk_lsi: clk-lsi { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <32000>; 70 }; 71 72 clk_msi: clk-msi { 73 #clock-cells = <0>; 74 compatible = "fixed-clock"; 75 clock-frequency = <4000000>; 76 }; 77 78 clk_i2sin: clk-i2sin { 79 #clock-cells = <0>; 80 compatible = "fixed-clock"; 81 clock-frequency = <0>; 82 }; 83 84 clk_rcbsec: clk-rcbsec { 85 #clock-cells = <0>; 86 compatible = "fixed-clock"; 87 clock-frequency = <64000000>; 88 }; 89 }; 90 91 soc@0 { 92 compatible = "simple-bus"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 interrupt-parent = <&intc>; 96 ranges = <0x0 0x0 0x0 0x80000000>; 97 98 hpdma1: dma-controller@40400000 { 99 compatible = "st,stm32-dma3"; 100 reg = <0x40400000 0x1000>; 101 clocks = <&rcc CK_BUS_HPDMA1>; 102 resets = <&rcc HPDMA1_R>; 103 #dma-cells = <4>; 104 status = "disabled"; 105 }; 106 107 hpdma2: dma-controller@40410000 { 108 compatible = "st,stm32-dma3"; 109 reg = <0x40410000 0x1000>; 110 clocks = <&rcc CK_BUS_HPDMA2>; 111 resets = <&rcc HPDMA2_R>; 112 #dma-cells = <4>; 113 status = "disabled"; 114 }; 115 116 hpdma3: dma-controller@40420000 { 117 compatible = "st,stm32-dma3"; 118 reg = <0x40420000 0x1000>; 119 clocks = <&rcc CK_BUS_HPDMA3>; 120 resets = <&rcc HPDMA3_R>; 121 #dma-cells = <4>; 122 status = "disabled"; 123 }; 124 125 ipcc1: mailbox@40490000 { 126 compatible = "st,stm32mp25-ipcc"; 127 reg = <0x40490000 0x400>; 128 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 129 interrupt-names = "rx"; 130 clocks = <&rcc CK_BUS_IPCC1>; 131 status = "disabled"; 132 }; 133 134 ommanager: ommanager@40500000 { 135 compatible = "st,stm32mp25-omm"; 136 reg = <0x40500000 0x400>, <0x60000000 0x10000000>; 137 reg-names = "regs", "memory_map"; 138 ranges = <0 0 0x40430000 0x400>, 139 <1 0 0x40440000 0x400>; 140 clocks = <&rcc CK_BUS_OSPIIOM>; 141 resets = <&rcc OSPIIOM_R>; 142 #address-cells = <2>; 143 #size-cells = <1>; 144 st,syscfg-amcr = <&syscfg 0x2c00 0x7>; 145 status = "disabled"; 146 147 ospi1: spi@0 { 148 compatible = "st,stm32mp25-ospi"; 149 reg = <0 0 0x400>; 150 clocks = <&rcc CK_KER_OSPI1>; 151 resets = <&rcc OSPI1_R>, <&rcc OSPI1DLL_R>; 152 status = "disabled"; 153 }; 154 155 ospi2: spi@1 { 156 compatible = "st,stm32mp25-ospi"; 157 reg = <1 0 0x400>; 158 clocks = <&rcc CK_KER_OSPI2>; 159 resets = <&rcc OSPI2_R>, <&rcc OSPI2DLL_R>; 160 status = "disabled"; 161 }; 162 }; 163 164 rifsc: bus@42080000 { 165 compatible = "st,stm32mp25-rifsc", "simple-bus"; 166 reg = <0x42080000 0x1000>; 167 #address-cells = <1>; 168 #size-cells = <1>; 169 #access-controller-cells = <1>; 170 171 usart2: serial@400e0000 { 172 compatible = "st,stm32h7-uart"; 173 reg = <0x400e0000 0x400>; 174 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&rcc CK_KER_USART2>; 176 access-controllers = <&rifsc STM32MP25_RIFSC_USART2_ID>; 177 status = "disabled"; 178 }; 179 180 i2c1: i2c@40120000 { 181 compatible = "st,stm32mp25-i2c"; 182 reg = <0x40120000 0x400>; 183 clocks = <&rcc CK_KER_I2C1>; 184 resets = <&rcc I2C1_R>; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 access-controllers = <&rifsc STM32MP25_RIFSC_I2C1_ID>; 188 status = "disabled"; 189 }; 190 191 i2c2: i2c@40130000 { 192 compatible = "st,stm32mp25-i2c"; 193 reg = <0x40130000 0x400>; 194 clocks = <&rcc CK_KER_I2C2>; 195 resets = <&rcc I2C2_R>; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 access-controllers = <&rifsc STM32MP25_RIFSC_I2C2_ID>; 199 status = "disabled"; 200 }; 201 202 i2c7: i2c@40180000 { 203 compatible = "st,stm32mp25-i2c"; 204 reg = <0x40180000 0x400>; 205 clocks = <&rcc CK_KER_I2C7>; 206 resets = <&rcc I2C7_R>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 access-controllers = <&rifsc STM32MP25_RIFSC_I2C7_ID>; 210 status = "disabled"; 211 }; 212 213 rng: rng@42020000 { 214 compatible = "st,stm32mp25-rng"; 215 reg = <0x42020000 0x400>; 216 clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; 217 clock-names = "rng_clk", "rng_hclk"; 218 resets = <&rcc RNG_R>; 219 access-controllers = <&rifsc STM32MP25_RIFSC_RNG_ID>; 220 }; 221 222 iwdg1: watchdog@44010000 { 223 compatible = "st,stm32mp1-iwdg"; 224 reg = <0x44010000 0x400>; 225 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&rcc CK_BUS_IWDG1>, <&rcc LSI_CK>; 227 clock-names = "pclk", "lsi"; 228 access-controllers = <&rifsc STM32MP25_RIFSC_IWDG1_ID>; 229 status = "disabled"; 230 }; 231 232 iwdg2: watchdog@44020000 { 233 compatible = "st,stm32mp1-iwdg"; 234 reg = <0x44020000 0x400>; 235 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&rcc CK_BUS_IWDG2>, <&rcc LSI_CK>; 237 clock-names = "pclk", "lsi"; 238 resets = <&rcc IWDG2_SYS_R>; 239 access-controllers = <&rifsc STM32MP25_RIFSC_IWDG2_ID>; 240 status = "disabled"; 241 }; 242 243 i2c8: i2c@46040000 { 244 compatible = "st,stm32mp25-i2c"; 245 reg = <0x46040000 0x400>; 246 clocks = <&rcc CK_KER_I2C8>; 247 resets = <&rcc I2C8_R>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 access-controllers = <&rifsc STM32MP25_RIFSC_I2C8_ID>; 251 status = "disabled"; 252 }; 253 }; 254 255 iac: iac@42090000 { 256 compatible = "st,stm32mp25-iac"; 257 reg = <0x42090000 0x400>; 258 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 259 }; 260 261 risaf1: risaf@420a0000 { 262 compatible = "st,stm32mp25-risaf"; 263 reg = <0x420a0000 0x1000>; 264 clocks = <&rcc CK_BUS_BKPSRAM>; 265 st,mem-map = <0x0 0x42000000 0x0 0x2000>; 266 #access-controller-cells = <1>; 267 }; 268 269 risaf2: risaf@420b0000 { 270 compatible = "st,stm32mp25-risaf"; 271 reg = <0x420b0000 0x1000>; 272 clocks = <&rcc CK_KER_OSPI1>; 273 st,mem-map = <0x0 0x60000000 0x0 0x10000000>; 274 #access-controller-cells = <1>; 275 status = "disabled"; 276 }; 277 278 risaf4: risaf@420d0000 { 279 compatible = "st,stm32mp25-risaf-enc"; 280 reg = <0x420d0000 0x1000>; 281 clocks = <&rcc CK_BUS_RISAF4>; 282 st,mem-map = <0x0 0x80000000 0x1 0x00000000>; 283 #access-controller-cells = <1>; 284 }; 285 286 risab1: risab@420f0000 { 287 compatible = "st,stm32mp25-risab"; 288 reg = <0x420f0000 0x1000>; 289 clocks = <&rcc CK_ICN_LS_MCU>; 290 st,mem-map = <0xa000000 0x20000>; 291 #access-controller-cells = <1>; 292 }; 293 294 risab2: risab@42100000 { 295 compatible = "st,stm32mp25-risab"; 296 reg = <0x42100000 0x1000>; 297 clocks = <&rcc CK_ICN_LS_MCU>; 298 st,mem-map = <0xa020000 0x20000>; 299 #access-controller-cells = <1>; 300 }; 301 302 risab3: risab@42110000 { 303 compatible = "st,stm32mp25-risab"; 304 reg = <0x42110000 0x1000>; 305 clocks = <&rcc CK_ICN_LS_MCU>; 306 st,mem-map = <0xa040000 0x20000>; 307 #access-controller-cells = <1>; 308 }; 309 310 risab4: risab@42120000 { 311 compatible = "st,stm32mp25-risab"; 312 reg = <0x42120000 0x1000>; 313 clocks = <&rcc CK_ICN_LS_MCU>; 314 st,mem-map = <0xa060000 0x20000>; 315 #access-controller-cells = <1>; 316 }; 317 318 risab5: risab@42130000 { 319 compatible = "st,stm32mp25-risab"; 320 reg = <0x42130000 0x1000>; 321 clocks = <&rcc CK_ICN_LS_MCU>; 322 st,mem-map = <0xa080000 0x20000>; 323 #access-controller-cells = <1>; 324 }; 325 326 risab6: risab@42140000 { 327 compatible = "st,stm32mp25-risab"; 328 reg = <0x42140000 0x1000>; 329 clocks = <&rcc CK_ICN_LS_MCU>; 330 st,mem-map = <0xa0a0000 0x20000>; 331 #access-controller-cells = <1>; 332 status = "disabled"; 333 }; 334 335 serc: serc@44080000 { 336 compatible = "st,stm32mp25-serc"; 337 reg = <0x44080000 0x1000>; 338 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&rcc CK_BUS_SERC>; 340 }; 341 342 rcc: rcc@44200000 { 343 compatible = "st,stm32mp25-rcc", "syscon"; 344 reg = <0x44200000 0x10000>; 345 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 346 347 #clock-cells = <1>; 348 #reset-cells = <1>; 349 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, 350 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>; 351 clock-names = "clk-hse", "clk-hsi", "clk-lse", 352 "clk-lsi", "clk-msi", "clk-i2sin"; 353 354 hsi_calibration: hsi-calibration { 355 compatible = "st,hsi-cal"; 356 st,cal_hsi_dev = <31>; 357 st,cal_hsi_ref = <1953>; 358 status = "disabled"; 359 }; 360 361 msi_calibration: msi-calibration { 362 compatible = "st,msi-cal"; 363 status = "disabled"; 364 }; 365 }; 366 367 exti1: interrupt-controller@44220000 { 368 compatible = "st,stm32mp1-exti"; 369 interrupt-controller; 370 #interrupt-cells = <2>; 371 reg = <0x44220000 0x400>; 372 interrupts-extended = 373 <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 374 <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 375 <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 376 <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 377 <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 378 <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 379 <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 380 <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 381 <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 382 <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 383 <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 384 <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 385 <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 386 <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 387 <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 388 <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 389 <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 390 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 391 <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 392 <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 393 <0>, /* EXTI_20 */ 394 <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 395 <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 396 <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 397 <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 398 <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 399 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 400 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 401 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 402 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 403 <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 404 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 405 <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 406 <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 407 <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 408 <0>, 409 <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 410 <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 411 <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 412 <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 413 <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 414 <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 415 <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 416 <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 417 <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 418 <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 419 <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 420 <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 421 <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 422 <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 423 <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 424 <0>, 425 <0>, 426 <0>, 427 <0>, 428 <0>, 429 <0>, 430 <0>, 431 <0>, 432 <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 433 <0>, /* EXTI_60 */ 434 <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 435 <0>, 436 <0>, 437 <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 438 <0>, 439 <0>, 440 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 441 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 442 <0>, 443 <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 444 <0>, 445 <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 446 <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 447 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 448 <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 449 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 450 <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 451 <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 452 <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 453 <0>, /* EXTI_80 */ 454 <0>, 455 <0>, 456 <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 457 <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 458 }; 459 460 syscfg: syscon@44230000 { 461 reg = <0x44230000 0x10000>; 462 status = "disabled"; 463 }; 464 465 pinctrl: pinctrl@44240000 { 466 #address-cells = <1>; 467 #size-cells = <1>; 468 compatible = "st,stm32mp257-pinctrl"; 469 ranges = <0 0x44240000 0xa0400>; 470 471 gpioa: gpio@44240000 { 472 gpio-controller; 473 #gpio-cells = <2>; 474 interrupt-controller; 475 #interrupt-cells = <2>; 476 #access-controller-cells = <1>; 477 reg = <0x0 0x400>; 478 clocks = <&rcc CK_BUS_GPIOA>; 479 st,bank-name = "GPIOA"; 480 status = "disabled"; 481 }; 482 483 gpiob: gpio@44250000 { 484 gpio-controller; 485 #gpio-cells = <2>; 486 interrupt-controller; 487 #interrupt-cells = <2>; 488 #access-controller-cells = <1>; 489 reg = <0x10000 0x400>; 490 clocks = <&rcc CK_BUS_GPIOB>; 491 st,bank-name = "GPIOB"; 492 status = "disabled"; 493 }; 494 495 gpioc: gpio@44260000 { 496 gpio-controller; 497 #gpio-cells = <2>; 498 interrupt-controller; 499 #interrupt-cells = <2>; 500 #access-controller-cells = <1>; 501 reg = <0x20000 0x400>; 502 clocks = <&rcc CK_BUS_GPIOC>; 503 st,bank-name = "GPIOC"; 504 status = "disabled"; 505 }; 506 507 gpiod: gpio@44270000 { 508 gpio-controller; 509 #gpio-cells = <2>; 510 interrupt-controller; 511 #interrupt-cells = <2>; 512 #access-controller-cells = <1>; 513 reg = <0x30000 0x400>; 514 clocks = <&rcc CK_BUS_GPIOD>; 515 st,bank-name = "GPIOD"; 516 status = "disabled"; 517 }; 518 519 gpioe: gpio@44280000 { 520 gpio-controller; 521 #gpio-cells = <2>; 522 interrupt-controller; 523 #interrupt-cells = <2>; 524 #access-controller-cells = <1>; 525 reg = <0x40000 0x400>; 526 clocks = <&rcc CK_BUS_GPIOE>; 527 st,bank-name = "GPIOE"; 528 status = "disabled"; 529 }; 530 531 gpiof: gpio@44290000 { 532 gpio-controller; 533 #gpio-cells = <2>; 534 interrupt-controller; 535 #interrupt-cells = <2>; 536 #access-controller-cells = <1>; 537 reg = <0x50000 0x400>; 538 clocks = <&rcc CK_BUS_GPIOF>; 539 st,bank-name = "GPIOF"; 540 status = "disabled"; 541 }; 542 543 gpiog: gpio@442a0000 { 544 gpio-controller; 545 #gpio-cells = <2>; 546 interrupt-controller; 547 #interrupt-cells = <2>; 548 #access-controller-cells = <1>; 549 reg = <0x60000 0x400>; 550 clocks = <&rcc CK_BUS_GPIOG>; 551 st,bank-name = "GPIOG"; 552 status = "disabled"; 553 }; 554 555 gpioh: gpio@442b0000 { 556 gpio-controller; 557 #gpio-cells = <2>; 558 interrupt-controller; 559 #interrupt-cells = <2>; 560 #access-controller-cells = <1>; 561 reg = <0x70000 0x400>; 562 clocks = <&rcc CK_BUS_GPIOH>; 563 st,bank-name = "GPIOH"; 564 status = "disabled"; 565 }; 566 567 gpioi: gpio@442c0000 { 568 gpio-controller; 569 #gpio-cells = <2>; 570 interrupt-controller; 571 #interrupt-cells = <2>; 572 #access-controller-cells = <1>; 573 reg = <0x80000 0x400>; 574 clocks = <&rcc CK_BUS_GPIOI>; 575 st,bank-name = "GPIOI"; 576 status = "disabled"; 577 }; 578 }; 579 580 rtc: rtc@46000000 { 581 compatible = "st,stm32mp25-rtc"; 582 reg = <0x46000000 0x400>; 583 clocks = <&rcc CK_BUS_RTC>, <&rcc RTC_CK>; 584 clock-names = "pclk", "rtc_ck"; 585 wakeup-source; 586 interrupts-extended = <&exti2 22 IRQ_TYPE_EDGE_RISING>; 587 }; 588 589 tamp: tamp@46010000 { 590 compatible = "st,stm32mp23-tamp"; 591 reg = <0x46010000 0x400>; 592 clocks = <&rcc CK_BUS_RTC>; 593 interrupts-extended = <&exti2 21 IRQ_TYPE_EDGE_RISING>; 594 #address-cells = <1>; 595 #size-cells = <1>; 596 ranges; 597 st,backup-zones = <24 24 24 24 12 12 8>; 598 }; 599 600 pinctrl_z: pinctrl-z@46200000 { 601 #address-cells = <1>; 602 #size-cells = <1>; 603 compatible = "st,stm32mp257-z-pinctrl"; 604 ranges = <0 0x46200000 0x400>; 605 606 gpioz: gpio@46200000 { 607 gpio-controller; 608 #gpio-cells = <2>; 609 interrupt-controller; 610 #interrupt-cells = <2>; 611 #access-controller-cells = <1>; 612 reg = <0 0x400>; 613 clocks = <&rcc CK_BUS_GPIOZ>; 614 st,bank-name = "GPIOZ"; 615 st,bank-ioport = <11>; 616 status = "disabled"; 617 }; 618 }; 619 620 exti2: interrupt-controller@46230000 { 621 compatible = "st,stm32mp1-exti"; 622 interrupt-controller; 623 #interrupt-cells = <2>; 624 reg = <0x46230000 0x400>; 625 interrupts-extended = 626 <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 627 <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 628 <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 629 <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 630 <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 631 <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 632 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 633 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 634 <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 635 <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 636 <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 637 <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 638 <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 639 <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 640 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 641 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 642 <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 643 <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 644 <0>, 645 <0>, 646 <0>, /* EXTI_20 */ 647 <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 648 <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 649 <0>, 650 <0>, 651 <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 652 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 653 <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 654 <0>, 655 <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 656 <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 657 <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 658 <0>, 659 <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 660 <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 661 <0>, 662 <0>, 663 <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 664 <0>, 665 <0>, 666 <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 667 <0>, 668 <0>, 669 <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 670 <0>, 671 <0>, 672 <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 673 <0>, 674 <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 675 <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 676 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 677 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 678 <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 679 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 680 <0>, 681 <0>, 682 <0>, 683 <0>, 684 <0>, 685 <0>, 686 <0>, /* EXTI_60 */ 687 <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 688 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 689 <0>, 690 <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 691 <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 692 <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 693 <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 694 <0>, 695 <0>, 696 <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 697 }; 698 699 hsem: hwspinlock@46240000 { 700 compatible = "st,stm32mp25-hsem"; 701 reg = <0x46240000 0x400>; 702 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&rcc CK_BUS_HSEM>; 704 }; 705 706 stgenc: stgen@48080000 { 707 compatible = "st,stm32mp25-stgen"; 708 reg = <0x48080000 0x1000>; 709 clocks = <&rcc CK_BUS_STGEN>, <&rcc CK_KER_STGEN>; 710 clock-names = "bus", "stgen_clk"; 711 }; 712 713 fmc: memory-controller@48200000 { 714 compatible = "st,stm32mp25-fmc2-ebi"; 715 reg = <0x48200000 0x400>; 716 ranges = <0 0 0x70000000 0x04000000>, /* EBI CS 1 */ 717 <1 0 0x74000000 0x04000000>, /* EBI CS 2 */ 718 <2 0 0x78000000 0x04000000>, /* EBI CS 3 */ 719 <3 0 0x7c000000 0x04000000>, /* EBI CS 4 */ 720 <4 0 0x48810000 0x00001000>; /* NAND */ 721 #address-cells = <2>; 722 #size-cells = <1>; 723 clocks = <&rcc CK_KER_FMC>; 724 resets = <&rcc FMC_R>; 725 status = "disabled"; 726 }; 727 }; 728}; 729