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Searched refs:reg_base (Results 1 – 25 of 427) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/gpio/
H A Dgpio-bcm-kona.c67 void __iomem *reg_base; member
83 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base, in bcm_kona_gpio_write_lock_regs() argument
86 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET); in bcm_kona_gpio_write_lock_regs()
87 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_write_lock_regs()
99 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_lock_gpio()
101 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); in bcm_kona_gpio_lock_gpio()
115 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_unlock_gpio()
117 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); in bcm_kona_gpio_unlock_gpio()
125 void __iomem *reg_base = kona_gpio->reg_base; in bcm_kona_gpio_get_dir() local
128 val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK; in bcm_kona_gpio_get_dir()
[all …]
H A Dgpio-amdpt.c27 void __iomem *reg_base; member
40 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_request()
48 writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_request()
63 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_free()
65 writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_free()
89 pt_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0); in pt_gpio_probe()
90 if (IS_ERR(pt_gpio->reg_base)) { in pt_gpio_probe()
92 return PTR_ERR(pt_gpio->reg_base); in pt_gpio_probe()
96 pt_gpio->reg_base + PT_INPUTDATA_REG, in pt_gpio_probe()
97 pt_gpio->reg_base + PT_OUTPUTDATA_REG, NULL, in pt_gpio_probe()
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/OK3568_Linux_fs/kernel/arch/sh/drivers/pci/
H A Dpci-sh7780.c100 addr = __raw_readl(hose->reg_base + SH4_PCIALR); in sh7780_pci_err_irq()
105 status = __raw_readw(hose->reg_base + PCI_STATUS); in sh7780_pci_err_irq()
113 __raw_writew(cmd, hose->reg_base + PCI_STATUS); in sh7780_pci_err_irq()
119 status = __raw_readl(hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
127 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
132 status = __raw_readl(hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
140 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
154 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM); in sh7780_pci_serr_irq()
169 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
177 PCI_STATUS_PARITY, hose->reg_base + PCI_STATUS); in sh7780_pci_setup_irqs()
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/OK3568_Linux_fs/u-boot/drivers/spi/
H A Dcadence_qspi_apb.c165 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \ argument
166 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
169 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \ argument
170 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
186 void cadence_qspi_apb_controller_enable(void *reg_base) in cadence_qspi_apb_controller_enable() argument
189 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
191 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
194 void cadence_qspi_apb_controller_disable(void *reg_base) in cadence_qspi_apb_controller_disable() argument
197 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
199 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
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/OK3568_Linux_fs/external/mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu540c.c454 regs->reg_base.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu540c_prep()
455 regs->reg_base.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; in setup_vepu540c_prep()
456 regs->reg_base.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu540c_prep()
457 regs->reg_base.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; in setup_vepu540c_prep()
461 regs->reg_base.src_fmt.src_cfmt = hw_fmt; in setup_vepu540c_prep()
462 regs->reg_base.src_fmt.alpha_swap = cfg.alpha_swap; in setup_vepu540c_prep()
463 regs->reg_base.src_fmt.rbuv_swap = cfg.rbuv_swap; in setup_vepu540c_prep()
465 regs->reg_base.src_fmt.out_fmt = 1; in setup_vepu540c_prep()
474 regs->reg_base.src_udfy.csc_wgt_b2y = 25; in setup_vepu540c_prep()
475 regs->reg_base.src_udfy.csc_wgt_g2y = 129; in setup_vepu540c_prep()
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H A Dhal_h264e_vepu580.c350 p->osd_cfg.reg_base = &p->regs_sets->reg_osd; in hal_h264e_vepu580_init()
580 ctx->osd_cfg.reg_base = &ctx->regs_set->reg_osd; in hal_h264e_vepu580_get_task()
699 regs->reg_base.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu580_prep()
700 regs->reg_base.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; in setup_vepu580_prep()
701 regs->reg_base.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu580_prep()
702 regs->reg_base.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; in setup_vepu580_prep()
706 regs->reg_base.src_fmt.src_cfmt = hw_fmt; in setup_vepu580_prep()
707 regs->reg_base.src_fmt.alpha_swap = cfg.alpha_swap; in setup_vepu580_prep()
708 regs->reg_base.src_fmt.rbuv_swap = cfg.rbuv_swap; in setup_vepu580_prep()
709 regs->reg_base.src_fmt.src_range = (prep->range == MPP_FRAME_RANGE_JPEG ? 1 : 0); in setup_vepu580_prep()
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/OK3568_Linux_fs/kernel/drivers/irqchip/
H A Dirq-csky-apb-intc.c34 static void __iomem *reg_base; variable
60 static void __init ck_set_gc(struct device_node *node, void __iomem *reg_base, in ck_set_gc() argument
66 gc->reg_base = reg_base; in ck_set_gc()
111 reg_base = of_iomap(node, 0); in ck_intc_init_comm()
112 if (!reg_base) { in ck_intc_init_comm()
153 readl(reg_base + GX_INTC_PEN63_32), 32); in gx_irq_handler()
158 readl(reg_base + GX_INTC_PEN31_00), 0); in gx_irq_handler()
175 writel(0x0, reg_base + GX_INTC_NEN31_00); in gx_intc_init()
176 writel(0x0, reg_base + GX_INTC_NEN63_32); in gx_intc_init()
181 writel(0x0, reg_base + GX_INTC_NMASK31_00); in gx_intc_init()
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/cavium/thunder/
H A Dthunder_xcv.c47 void __iomem *reg_base; member
70 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
75 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
84 cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
87 writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
92 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
94 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
95 readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
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/OK3568_Linux_fs/kernel/drivers/ata/
H A Dahci_qoriq.c63 struct ccsr_ahci *reg_base; member
173 void __iomem *reg_base = hpriv->mmio; in ahci_qoriq_phy_init() local
181 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); in ahci_qoriq_phy_init()
182 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2); in ahci_qoriq_phy_init()
183 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3); in ahci_qoriq_phy_init()
184 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4); in ahci_qoriq_phy_init()
185 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5); in ahci_qoriq_phy_init()
186 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); in ahci_qoriq_phy_init()
189 reg_base + LS1021A_AXICC_ADDR); in ahci_qoriq_phy_init()
199 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); in ahci_qoriq_phy_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/devfreq/event/
H A Drockchip-nocp.c43 void __iomem *reg_base; member
55 void __iomem *reg_base = nocp->reg_base; in rockchip_nocp_enable() local
57 writel_relaxed(GLOBAL_EN, reg_base + PROBE_CFGCTL); in rockchip_nocp_enable()
58 writel_relaxed(START_EN, reg_base + PROBE_MAINCTL); in rockchip_nocp_enable()
59 writel_relaxed(0, reg_base + PROBE_STATPERIOD); in rockchip_nocp_enable()
60 writel_relaxed(EVENT_BYTE, reg_base + info->counter0_src); in rockchip_nocp_enable()
61 writel_relaxed(EVENT_CHAIN, reg_base + info->counter1_src); in rockchip_nocp_enable()
62 writel_relaxed(START_GO, reg_base + PROBE_STATGO); in rockchip_nocp_enable()
73 void __iomem *reg_base = nocp->reg_base; in rockchip_nocp_disable() local
75 writel_relaxed(0, reg_base + PROBE_STATGO); in rockchip_nocp_disable()
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/OK3568_Linux_fs/kernel/drivers/remoteproc/
H A Dqcom_q6v5_wcss.c77 void __iomem *reg_base; member
107 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
109 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
112 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
114 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
117 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, in q6v5_wcss_reset()
126 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
128 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
133 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
136 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
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H A Dmtk_scp.c142 val = readl(scp->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_assert()
144 writel(val, scp->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_assert()
151 val = readl(scp->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_deassert()
153 writel(val, scp->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_deassert()
158 writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET); in mt8192_scp_reset_assert()
163 writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_CLR); in mt8192_scp_reset_deassert()
170 scp_to_host = readl(scp->reg_base + MT8183_SCP_TO_HOST); in mt8183_scp_irq_handler()
178 scp->reg_base + MT8183_SCP_TO_HOST); in mt8183_scp_irq_handler()
185 scp_to_host = readl(scp->reg_base + MT8192_SCP2APMCU_IPC_SET); in mt8192_scp_irq_handler()
195 scp->reg_base + MT8192_SCP2APMCU_IPC_CLR); in mt8192_scp_irq_handler()
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/mmp/hw/
H A Dmmp_spi.c34 void __iomem *reg_base = (void __iomem *) in lcd_spi_write() local
38 writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR); in lcd_spi_write()
42 writel_relaxed((u8)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
45 writel_relaxed((u16)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
48 writel_relaxed((u32)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
55 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
58 writel(tmp, reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
60 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
63 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
71 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
[all …]
/OK3568_Linux_fs/u-boot/board/sunxi/
H A Dahci.c17 static int sunxi_ahci_phy_init(u8 *reg_base) in sunxi_ahci_phy_init() argument
22 writel(0, reg_base + AHCI_RWCR); in sunxi_ahci_phy_init()
25 setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19); in sunxi_ahci_phy_init()
26 clrsetbits_le32(reg_base + AHCI_PHYCS0R, in sunxi_ahci_phy_init()
29 clrsetbits_le32(reg_base + AHCI_PHYCS1R, in sunxi_ahci_phy_init()
32 setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15)); in sunxi_ahci_phy_init()
33 clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19)); in sunxi_ahci_phy_init()
34 clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20)); in sunxi_ahci_phy_init()
35 clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5)); in sunxi_ahci_phy_init()
38 setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19)); in sunxi_ahci_phy_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/ide/
H A Dopti621.c30 static int reg_base; variable
41 inw(reg_base + 1); in write_reg()
42 inw(reg_base + 1); in write_reg()
43 outb(3, reg_base + 2); in write_reg()
44 outb(value, reg_base + reg); in write_reg()
45 outb(0x83, reg_base + 2); in write_reg()
57 inw(reg_base + 1); in read_reg()
58 inw(reg_base + 1); in read_reg()
59 outb(3, reg_base + 2); in read_reg()
60 ret = inb(reg_base + reg); in read_reg()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/can/
H A Dkvaser_pciefd.c259 void __iomem *reg_base; member
272 void __iomem *reg_base; member
333 ret = readl_poll_timeout(pcie->reg_base + KVASER_PCIEFD_SPI_STATUS_REG, in kvaser_pciefd_spi_wait_loop()
344 iowrite32(BIT(0), pcie->reg_base + KVASER_PCIEFD_SPI_SSEL_REG); in kvaser_pciefd_spi_cmd()
345 iowrite32(BIT(10), pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG); in kvaser_pciefd_spi_cmd()
346 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG); in kvaser_pciefd_spi_cmd()
353 iowrite32(*tx++, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG); in kvaser_pciefd_spi_cmd()
358 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG); in kvaser_pciefd_spi_cmd()
366 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG); in kvaser_pciefd_spi_cmd()
371 *rx++ = ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG); in kvaser_pciefd_spi_cmd()
[all …]
/OK3568_Linux_fs/kernel/drivers/spi/
H A Dspi-fsl-spi.c93 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_change_mode() local
94 __be32 __iomem *mode = &reg_base->mode; in fsl_spi_change_mode()
293 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_bufs() local
298 mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE); in fsl_spi_cpu_bufs()
302 mpc8xxx_spi_write_reg(&reg_base->transmit, word); in fsl_spi_cpu_bufs()
311 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_bufs() local
316 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_bufs()
349 mpc8xxx_spi_write_reg(&reg_base->mask, 0); in fsl_spi_bufs()
442 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_setup() local
460 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_setup()
[all …]
/OK3568_Linux_fs/kernel/drivers/rtc/
H A Drtc-zynqmp.c46 void __iomem *reg_base; member
69 writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR)); in xlnx_rtc_set_time()
71 writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); in xlnx_rtc_set_time()
81 writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_set_time()
92 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_read_time()
99 read_time = readl(xrtcdev->reg_base + RTC_CUR_TM); in xlnx_rtc_read_time()
108 read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1; in xlnx_rtc_read_time()
119 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time); in xlnx_rtc_read_alarm()
120 alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM; in xlnx_rtc_read_alarm()
135 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_alarm_irq_enable()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/zte/
H A Dclk.c47 hw_cfg0 = readl_relaxed(zx_pll->reg_base); in hw_to_idx()
48 hw_cfg1 = readl_relaxed(zx_pll->reg_base + CFG0_CFG1_OFFSET); in hw_to_idx()
100 writel_relaxed(config->cfg0, zx_pll->reg_base); in zx_pll_set_rate()
101 writel_relaxed(config->cfg1, zx_pll->reg_base + CFG0_CFG1_OFFSET); in zx_pll_set_rate()
115 reg = readl_relaxed(zx_pll->reg_base); in zx_pll_enable()
116 writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base); in zx_pll_enable()
118 return readl_relaxed_poll_timeout(zx_pll->reg_base, reg, in zx_pll_enable()
130 reg = readl_relaxed(zx_pll->reg_base); in zx_pll_disable()
131 writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base); in zx_pll_disable()
139 reg = readl_relaxed(zx_pll->reg_base); in zx_pll_is_enabled()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/samsung/
H A Dclk-s5pv210-audss.c24 static void __iomem *reg_base; variable
43 reg_save[i][1] = readl(reg_base + reg_save[i][0]); in s5pv210_audss_clk_suspend()
53 writel(reg_save[i][1], reg_base + reg_save[i][0]); in s5pv210_audss_clk_resume()
74 reg_base = devm_ioremap_resource(&pdev->dev, res); in s5pv210_audss_clk_probe()
75 if (IS_ERR(reg_base)) { in s5pv210_audss_clk_probe()
77 return PTR_ERR(reg_base); in s5pv210_audss_clk_probe()
120 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in s5pv210_audss_clk_probe()
131 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); in s5pv210_audss_clk_probe()
135 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); in s5pv210_audss_clk_probe()
138 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); in s5pv210_audss_clk_probe()
[all …]
H A Dclk-exynos-audss.c22 static void __iomem *reg_base; variable
47 reg_save[i][1] = readl(reg_base + reg_save[i][0]); in exynos_audss_clk_suspend()
57 writel(reg_save[i][1], reg_base + reg_save[i][0]); in exynos_audss_clk_resume()
141 reg_base = devm_ioremap_resource(dev, res); in exynos_audss_clk_probe()
142 if (IS_ERR(reg_base)) in exynos_audss_clk_probe()
143 return PTR_ERR(reg_base); in exynos_audss_clk_probe()
189 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in exynos_audss_clk_probe()
200 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); in exynos_audss_clk_probe()
204 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); in exynos_audss_clk_probe()
208 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); in exynos_audss_clk_probe()
[all …]
/OK3568_Linux_fs/kernel/drivers/input/serio/
H A Dsun4i-ps2.c85 void __iomem *reg_base; member
107 intr_status = readl(drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
108 fifo_status = readl(drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
118 writel(rval, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
125 writel(rval, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
130 byte = readl(drvdata->reg_base + PS2_REG_DATA) & 0xff; in sun4i_ps2_interrupt()
134 writel(intr_status, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
135 writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
154 writel(rval, drvdata->reg_base + PS2_REG_LCTL); in sun4i_ps2_open()
161 writel(rval, drvdata->reg_base + PS2_REG_FCTL); in sun4i_ps2_open()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-rockchip/
H A Drockchip.c29 void __iomem *reg_base; in rockchip_timer_init() local
36 reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K); in rockchip_timer_init()
37 if (reg_base) { in rockchip_timer_init()
38 writel(0, reg_base + 0x30); in rockchip_timer_init()
39 writel(0xffffffff, reg_base + 0x20); in rockchip_timer_init()
40 writel(0xffffffff, reg_base + 0x24); in rockchip_timer_init()
41 writel(1, reg_base + 0x30); in rockchip_timer_init()
43 iounmap(reg_base); in rockchip_timer_init()
/OK3568_Linux_fs/kernel/arch/sparc/kernel/
H A Dsbus.c213 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sbus_build_irq() local
223 imap += reg_base; in sbus_build_irq()
238 iclr = reg_base + SYSIO_ICLR_SLOT0; in sbus_build_irq()
241 iclr = reg_base + SYSIO_ICLR_SLOT1; in sbus_build_irq()
244 iclr = reg_base + SYSIO_ICLR_SLOT2; in sbus_build_irq()
248 iclr = reg_base + SYSIO_ICLR_SLOT3; in sbus_build_irq()
275 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ue_handler() local
280 afsr_reg = reg_base + SYSIO_UE_AFSR; in sysio_ue_handler()
281 afar_reg = reg_base + SYSIO_UE_AFAR; in sysio_ue_handler()
349 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ce_handler() local
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/
H A Dns16550.c31 static unsigned char *reg_base; variable
36 out_8(reg_base + (UART_FCR << reg_shift), 0x06); in ns16550_open()
42 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_THRE) == 0); in ns16550_putc()
43 out_8(reg_base, c); in ns16550_putc()
48 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0); in ns16550_getc()
49 return in_8(reg_base); in ns16550_getc()
54 return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0); in ns16550_tstc()
62 if (dt_get_virtual_reg(devp, (void **)&reg_base, 1) < 1) { in ns16550_console_init()
69 reg_base += be32_to_cpu(reg_offset); in ns16550_console_init()

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