165 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base)			\  argument
166 	(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>	\
169 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base)			\  argument
170 	(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>	\
186 void cadence_qspi_apb_controller_enable(void *reg_base)  in cadence_qspi_apb_controller_enable()  argument
189 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_controller_enable()
191 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_controller_enable()
194 void cadence_qspi_apb_controller_disable(void *reg_base)  in cadence_qspi_apb_controller_disable()  argument
197 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_controller_disable()
199 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_controller_disable()
203 static unsigned int cadence_qspi_wait_idle(void *reg_base)  in cadence_qspi_wait_idle()  argument
211 		if (CQSPI_REG_IS_IDLE(reg_base))  in cadence_qspi_wait_idle()
229 void cadence_qspi_apb_readdata_capture(void *reg_base,  in cadence_qspi_apb_readdata_capture()  argument
233 	cadence_qspi_apb_controller_disable(reg_base);  in cadence_qspi_apb_readdata_capture()
235 	reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);  in cadence_qspi_apb_readdata_capture()
248 	writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);  in cadence_qspi_apb_readdata_capture()
250 	cadence_qspi_apb_controller_enable(reg_base);  in cadence_qspi_apb_readdata_capture()
253 void cadence_qspi_apb_config_baudrate_div(void *reg_base,  in cadence_qspi_apb_config_baudrate_div()  argument
259 	cadence_qspi_apb_controller_disable(reg_base);  in cadence_qspi_apb_config_baudrate_div()
260 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_config_baudrate_div()
278 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_config_baudrate_div()
280 	cadence_qspi_apb_controller_enable(reg_base);  in cadence_qspi_apb_config_baudrate_div()
283 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)  in cadence_qspi_apb_set_clk_mode()  argument
287 	cadence_qspi_apb_controller_disable(reg_base);  in cadence_qspi_apb_set_clk_mode()
288 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_set_clk_mode()
296 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_set_clk_mode()
298 	cadence_qspi_apb_controller_enable(reg_base);  in cadence_qspi_apb_set_clk_mode()
301 void cadence_qspi_apb_chipselect(void *reg_base,  in cadence_qspi_apb_chipselect()  argument
306 	cadence_qspi_apb_controller_disable(reg_base);  in cadence_qspi_apb_chipselect()
311 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_chipselect()
330 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_chipselect()
332 	cadence_qspi_apb_controller_enable(reg_base);  in cadence_qspi_apb_chipselect()
335 void cadence_qspi_apb_delay(void *reg_base,  in cadence_qspi_apb_delay()  argument
345 	cadence_qspi_apb_controller_disable(reg_base);  in cadence_qspi_apb_delay()
371 	writel(reg, reg_base + CQSPI_REG_DELAY);  in cadence_qspi_apb_delay()
373 	cadence_qspi_apb_controller_enable(reg_base);  in cadence_qspi_apb_delay()
403 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,  in cadence_qspi_apb_exec_flash_cmd()  argument
409 	writel(reg, reg_base + CQSPI_REG_CMDCTRL);  in cadence_qspi_apb_exec_flash_cmd()
412 	writel(reg, reg_base + CQSPI_REG_CMDCTRL);  in cadence_qspi_apb_exec_flash_cmd()
415 		reg = readl(reg_base + CQSPI_REG_CMDCTRL);  in cadence_qspi_apb_exec_flash_cmd()
427 	if (!cadence_qspi_wait_idle(reg_base))  in cadence_qspi_apb_exec_flash_cmd()
434 int cadence_qspi_apb_command_read(void *reg_base,  in cadence_qspi_apb_command_read()  argument
455 	status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);  in cadence_qspi_apb_command_read()
459 	reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);  in cadence_qspi_apb_command_read()
467 		reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);  in cadence_qspi_apb_command_read()
476 int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,  in cadence_qspi_apb_command_write()  argument
502 		writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);  in cadence_qspi_apb_command_write()
513 		writel(wr_data, reg_base +  in cadence_qspi_apb_command_write()
520 			writel(wr_data, reg_base +  in cadence_qspi_apb_command_write()
526 	return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);  in cadence_qspi_apb_command_write()
772 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)  in cadence_qspi_apb_enter_xip()  argument
777 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_enter_xip()
781 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_enter_xip()
784 	writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);  in cadence_qspi_apb_enter_xip()
787 	reg = readl(reg_base + CQSPI_REG_RD_INSTR);  in cadence_qspi_apb_enter_xip()
789 	writel(reg, reg_base + CQSPI_REG_RD_INSTR);  in cadence_qspi_apb_enter_xip()