1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * 16550 serial console support.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Original copied from <file:arch/ppc/boot/common/ns16550.c>
6*4882a593Smuzhiyun * (which had no copyright)
7*4882a593Smuzhiyun * Modifications: 2006 (c) MontaVista Software, Inc.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Modified by: Mark A. Greer <mgreer@mvista.com>
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun #include <stdarg.h>
12*4882a593Smuzhiyun #include <stddef.h>
13*4882a593Smuzhiyun #include "types.h"
14*4882a593Smuzhiyun #include "string.h"
15*4882a593Smuzhiyun #include "stdio.h"
16*4882a593Smuzhiyun #include "io.h"
17*4882a593Smuzhiyun #include "ops.h"
18*4882a593Smuzhiyun #include "of.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define UART_DLL 0 /* Out: Divisor Latch Low */
21*4882a593Smuzhiyun #define UART_DLM 1 /* Out: Divisor Latch High */
22*4882a593Smuzhiyun #define UART_FCR 2 /* Out: FIFO Control Register */
23*4882a593Smuzhiyun #define UART_LCR 3 /* Out: Line Control Register */
24*4882a593Smuzhiyun #define UART_MCR 4 /* Out: Modem Control Register */
25*4882a593Smuzhiyun #define UART_LSR 5 /* In: Line Status Register */
26*4882a593Smuzhiyun #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
27*4882a593Smuzhiyun #define UART_LSR_DR 0x01 /* Receiver data ready */
28*4882a593Smuzhiyun #define UART_MSR 6 /* In: Modem Status Register */
29*4882a593Smuzhiyun #define UART_SCR 7 /* I/O: Scratch Register */
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun static unsigned char *reg_base;
32*4882a593Smuzhiyun static u32 reg_shift;
33*4882a593Smuzhiyun
ns16550_open(void)34*4882a593Smuzhiyun static int ns16550_open(void)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun out_8(reg_base + (UART_FCR << reg_shift), 0x06);
37*4882a593Smuzhiyun return 0;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
ns16550_putc(unsigned char c)40*4882a593Smuzhiyun static void ns16550_putc(unsigned char c)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_THRE) == 0);
43*4882a593Smuzhiyun out_8(reg_base, c);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
ns16550_getc(void)46*4882a593Smuzhiyun static unsigned char ns16550_getc(void)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0);
49*4882a593Smuzhiyun return in_8(reg_base);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
ns16550_tstc(void)52*4882a593Smuzhiyun static u8 ns16550_tstc(void)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
ns16550_console_init(void * devp,struct serial_console_data * scdp)57*4882a593Smuzhiyun int ns16550_console_init(void *devp, struct serial_console_data *scdp)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun int n;
60*4882a593Smuzhiyun u32 reg_offset;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1) {
63*4882a593Smuzhiyun printf("virt reg parse fail...\r\n");
64*4882a593Smuzhiyun return -1;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun n = getprop(devp, "reg-offset", ®_offset, sizeof(reg_offset));
68*4882a593Smuzhiyun if (n == sizeof(reg_offset))
69*4882a593Smuzhiyun reg_base += be32_to_cpu(reg_offset);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun n = getprop(devp, "reg-shift", ®_shift, sizeof(reg_shift));
72*4882a593Smuzhiyun if (n != sizeof(reg_shift))
73*4882a593Smuzhiyun reg_shift = 0;
74*4882a593Smuzhiyun else
75*4882a593Smuzhiyun reg_shift = be32_to_cpu(reg_shift);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun scdp->open = ns16550_open;
78*4882a593Smuzhiyun scdp->putc = ns16550_putc;
79*4882a593Smuzhiyun scdp->getc = ns16550_getc;
80*4882a593Smuzhiyun scdp->tstc = ns16550_tstc;
81*4882a593Smuzhiyun scdp->close = NULL;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return 0;
84*4882a593Smuzhiyun }
85