xref: /OK3568_Linux_fs/kernel/drivers/ide/opti621.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  Copyright (C) 1996-1998  Linus Torvalds & authors (see below)
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun /*
7*4882a593Smuzhiyun  * Authors:
8*4882a593Smuzhiyun  * Jaromir Koutek <miri@punknet.cz>,
9*4882a593Smuzhiyun  * Jan Harkes <jaharkes@cwi.nl>,
10*4882a593Smuzhiyun  * Mark Lord <mlord@pobox.com>
11*4882a593Smuzhiyun  * Some parts of code are from ali14xx.c and from rz1000.c.
12*4882a593Smuzhiyun  */
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <linux/types.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/pci.h>
18*4882a593Smuzhiyun #include <linux/ide.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include <asm/io.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define DRV_NAME "opti621"
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #define READ_REG 0	/* index of Read cycle timing register */
25*4882a593Smuzhiyun #define WRITE_REG 1	/* index of Write cycle timing register */
26*4882a593Smuzhiyun #define CNTRL_REG 3	/* index of Control register */
27*4882a593Smuzhiyun #define STRAP_REG 5	/* index of Strap register */
28*4882a593Smuzhiyun #define MISC_REG 6	/* index of Miscellaneous register */
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun static int reg_base;
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun static DEFINE_SPINLOCK(opti621_lock);
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun /* Write value to register reg, base of register
35*4882a593Smuzhiyun  * is at reg_base (0x1f0 primary, 0x170 secondary,
36*4882a593Smuzhiyun  * if not changed by PCI configuration).
37*4882a593Smuzhiyun  * This is from setupvic.exe program.
38*4882a593Smuzhiyun  */
write_reg(u8 value,int reg)39*4882a593Smuzhiyun static void write_reg(u8 value, int reg)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun 	inw(reg_base + 1);
42*4882a593Smuzhiyun 	inw(reg_base + 1);
43*4882a593Smuzhiyun 	outb(3, reg_base + 2);
44*4882a593Smuzhiyun 	outb(value, reg_base + reg);
45*4882a593Smuzhiyun 	outb(0x83, reg_base + 2);
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun /* Read value from register reg, base of register
49*4882a593Smuzhiyun  * is at reg_base (0x1f0 primary, 0x170 secondary,
50*4882a593Smuzhiyun  * if not changed by PCI configuration).
51*4882a593Smuzhiyun  * This is from setupvic.exe program.
52*4882a593Smuzhiyun  */
read_reg(int reg)53*4882a593Smuzhiyun static u8 read_reg(int reg)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	u8 ret = 0;
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	inw(reg_base + 1);
58*4882a593Smuzhiyun 	inw(reg_base + 1);
59*4882a593Smuzhiyun 	outb(3, reg_base + 2);
60*4882a593Smuzhiyun 	ret = inb(reg_base + reg);
61*4882a593Smuzhiyun 	outb(0x83, reg_base + 2);
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	return ret;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun 
opti621_set_pio_mode(ide_hwif_t * hwif,ide_drive_t * drive)66*4882a593Smuzhiyun static void opti621_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun 	ide_drive_t *pair = ide_get_pair_dev(drive);
69*4882a593Smuzhiyun 	unsigned long flags;
70*4882a593Smuzhiyun 	unsigned long mode = drive->pio_mode, pair_mode;
71*4882a593Smuzhiyun 	const u8 pio = mode - XFER_PIO_0;
72*4882a593Smuzhiyun 	u8 tim, misc, addr_pio = pio, clk;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	/* DRDY is default 2 (by OPTi Databook) */
75*4882a593Smuzhiyun 	static const u8 addr_timings[2][5] = {
76*4882a593Smuzhiyun 		{ 0x20, 0x10, 0x00, 0x00, 0x00 },	/* 33 MHz */
77*4882a593Smuzhiyun 		{ 0x10, 0x10, 0x00, 0x00, 0x00 },	/* 25 MHz */
78*4882a593Smuzhiyun 	};
79*4882a593Smuzhiyun 	static const u8 data_rec_timings[2][5] = {
80*4882a593Smuzhiyun 		{ 0x5b, 0x45, 0x32, 0x21, 0x20 },	/* 33 MHz */
81*4882a593Smuzhiyun 		{ 0x48, 0x34, 0x21, 0x10, 0x10 }	/* 25 MHz */
82*4882a593Smuzhiyun 	};
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	ide_set_drivedata(drive, (void *)mode);
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	if (pair) {
87*4882a593Smuzhiyun 		pair_mode = (unsigned long)ide_get_drivedata(pair);
88*4882a593Smuzhiyun 		if (pair_mode && pair_mode < mode)
89*4882a593Smuzhiyun 			addr_pio = pair_mode - XFER_PIO_0;
90*4882a593Smuzhiyun 	}
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	spin_lock_irqsave(&opti621_lock, flags);
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	reg_base = hwif->io_ports.data_addr;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	/* allow Register-B */
97*4882a593Smuzhiyun 	outb(0xc0, reg_base + CNTRL_REG);
98*4882a593Smuzhiyun 	/* hmm, setupvic.exe does this ;-) */
99*4882a593Smuzhiyun 	outb(0xff, reg_base + 5);
100*4882a593Smuzhiyun 	/* if reads 0xff, adapter not exist? */
101*4882a593Smuzhiyun 	(void)inb(reg_base + CNTRL_REG);
102*4882a593Smuzhiyun 	/* if reads 0xc0, no interface exist? */
103*4882a593Smuzhiyun 	read_reg(CNTRL_REG);
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	/* check CLK speed */
106*4882a593Smuzhiyun 	clk = read_reg(STRAP_REG) & 1;
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	printk(KERN_INFO "%s: CLK = %d MHz\n", hwif->name, clk ? 25 : 33);
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	tim  = data_rec_timings[clk][pio];
111*4882a593Smuzhiyun 	misc = addr_timings[clk][addr_pio];
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	/* select Index-0/1 for Register-A/B */
114*4882a593Smuzhiyun 	write_reg(drive->dn & 1, MISC_REG);
115*4882a593Smuzhiyun 	/* set read cycle timings */
116*4882a593Smuzhiyun 	write_reg(tim, READ_REG);
117*4882a593Smuzhiyun 	/* set write cycle timings */
118*4882a593Smuzhiyun 	write_reg(tim, WRITE_REG);
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	/* use Register-A for drive 0 */
121*4882a593Smuzhiyun 	/* use Register-B for drive 1 */
122*4882a593Smuzhiyun 	write_reg(0x85, CNTRL_REG);
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	/* set address setup, DRDY timings,   */
125*4882a593Smuzhiyun 	/*  and read prefetch for both drives */
126*4882a593Smuzhiyun 	write_reg(misc, MISC_REG);
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	spin_unlock_irqrestore(&opti621_lock, flags);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun static const struct ide_port_ops opti621_port_ops = {
132*4882a593Smuzhiyun 	.set_pio_mode		= opti621_set_pio_mode,
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun static const struct ide_port_info opti621_chipset = {
136*4882a593Smuzhiyun 	.name		= DRV_NAME,
137*4882a593Smuzhiyun 	.enablebits	= { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
138*4882a593Smuzhiyun 	.port_ops	= &opti621_port_ops,
139*4882a593Smuzhiyun 	.host_flags	= IDE_HFLAG_NO_DMA,
140*4882a593Smuzhiyun 	.pio_mask	= ATA_PIO4,
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun 
opti621_init_one(struct pci_dev * dev,const struct pci_device_id * id)143*4882a593Smuzhiyun static int opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun 	return ide_pci_init_one(dev, &opti621_chipset, NULL);
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun static const struct pci_device_id opti621_pci_tbl[] = {
149*4882a593Smuzhiyun 	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
150*4882a593Smuzhiyun 	{ PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 0 },
151*4882a593Smuzhiyun 	{ 0, },
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, opti621_pci_tbl);
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun static struct pci_driver opti621_pci_driver = {
156*4882a593Smuzhiyun 	.name		= "Opti621_IDE",
157*4882a593Smuzhiyun 	.id_table	= opti621_pci_tbl,
158*4882a593Smuzhiyun 	.probe		= opti621_init_one,
159*4882a593Smuzhiyun 	.remove		= ide_pci_remove,
160*4882a593Smuzhiyun 	.suspend	= ide_pci_suspend,
161*4882a593Smuzhiyun 	.resume		= ide_pci_resume,
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun 
opti621_ide_init(void)164*4882a593Smuzhiyun static int __init opti621_ide_init(void)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun 	return ide_pci_register_driver(&opti621_pci_driver);
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun 
opti621_ide_exit(void)169*4882a593Smuzhiyun static void __exit opti621_ide_exit(void)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun 	pci_unregister_driver(&opti621_pci_driver);
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun module_init(opti621_ide_init);
175*4882a593Smuzhiyun module_exit(opti621_ide_exit);
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun MODULE_AUTHOR("Jaromir Koutek, Jan Harkes, Mark Lord");
178*4882a593Smuzhiyun MODULE_DESCRIPTION("PCI driver module for Opti621 IDE");
179*4882a593Smuzhiyun MODULE_LICENSE("GPL");
180