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Searched refs:SCLK (Results 1 – 25 of 28) sorted by relevance

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/OK3568_Linux_fs/u-boot/board/renesas/stout/
H A Dcpld.c16 #define SCLK GPIO_GP_3_24 macro
35 gpio_set_value(SCLK, 1); in cpld_read()
37 gpio_set_value(SCLK, 0); in cpld_read()
42 gpio_set_value(SCLK, 1); in cpld_read()
43 gpio_set_value(SCLK, 0); in cpld_read()
47 gpio_set_value(SCLK, 1); in cpld_read()
50 gpio_set_value(SCLK, 0); in cpld_read()
62 gpio_set_value(SCLK, 1); in cpld_write()
64 gpio_set_value(SCLK, 0); in cpld_write()
69 gpio_set_value(SCLK, 1); in cpld_write()
[all …]
/OK3568_Linux_fs/u-boot/board/renesas/ulcb/
H A Dcpld.c15 #define SCLK GPIO_GP_6_8 macro
51 gpio_set_value(SCLK, set); in ulcb_softspi_scl()
63 gpio_set_value(SCLK, 1); in cpld_rw()
64 gpio_set_value(SCLK, 0); in cpld_rw()
100 gpio_request(SCLK, NULL); in cpld_init()
105 gpio_direction_output(SCLK, 0); in cpld_init()
/OK3568_Linux_fs/u-boot/drivers/rtc/
H A Dds1302.c16 #define SCLK 0x400 macro
20 #define RESET rtc_go_low(RST), rtc_go_low(SCLK)
21 #define N_RESET rtc_go_high(RST), rtc_go_low(SCLK)
23 #define CLOCK_HIGH rtc_go_high(SCLK)
24 #define CLOCK_LOW rtc_go_low(SCLK)
200 rtc_go_output(DATA|SCLK|RST); in rtc_init()
/OK3568_Linux_fs/kernel/drivers/spi/
H A Dspi-lm70llp.c66 #define SCLK 0x40 macro
116 parport_write_data(pp->port, data | SCLK); in clkHigh()
123 parport_write_data(pp->port, data & ~SCLK); in clkLow()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iio/resolver/
H A Dad2s90.txt19 application of SCLK, as also specified. And since the delay is not
20 implemented in the spi code, to satisfy it, SCLK's period should be at most
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Dpcm512x.txt19 - clocks : A clock specifier for the clock connected as SCLK. If this
27 external connection from the pll-out pin to the SCLK pin is assumed.
H A Dcs35l34.txt45 SCLK. Otherwise, data is on the falling edge of SCLK.
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dmicrochip,pic32-clock.h18 #define SCLK 7 macro
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/
H A Dspi_oc_tiny.txt9 the input clock to SCLK.
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/i2c/
H A Drenesas,iic-emev2.txt7 - clocks : phandle to the IP core SCLK
/OK3568_Linux_fs/kernel/Documentation/hwmon/
H A Dlm70.rst41 the driver accesses the LM70 using SPI communication: 16 SCLK cycles
/OK3568_Linux_fs/kernel/drivers/clk/microchip/
H A Dclk-pic32mzda.c210 clks[SCLK] = pic32_sys_clk_register(&sys_mux_clk, core); in pic32mzda_clk_probe()
/OK3568_Linux_fs/u-boot/include/
H A Dsym53c8xx.h188 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ macro
/OK3568_Linux_fs/kernel/Documentation/spi/
H A Dspi-lm70llp.rst45 D6 8 --> SCLK 3
H A Dspi-summary.rst184 physical SPI bus segment, with SCLK, MOSI, and MISO.
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Darmada-385-turris-omnia.dts345 /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */
/OK3568_Linux_fs/kernel/drivers/scsi/sym53c8xx_2/
H A Dsym_defs.h268 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ macro
/OK3568_Linux_fs/kernel/Documentation/input/devices/
H A Damijoy.rst102 the rising edge of SCLK. MLD output is used to parallel load
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Darmada-385-turris-omnia.dts377 /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3328-rock64-android.dtsi512 /* The max SCLK of the flash 104/80 MHZ */
/OK3568_Linux_fs/kernel/drivers/scsi/
H A Dncr53c8xx.h791 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c110 CLK_MAP(SCLK, CLOCK_GFXCLK),
/OK3568_Linux_fs/u-boot/drivers/video/
H A DKconfig362 string "SPI SCLK pin for LCD related config job"
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dnavi10_ppt.c150 CLK_MAP(SCLK, PPCLK_GFXCLK),
H A Darcturus_ppt.c149 CLK_MAP(SCLK, PPCLK_GFXCLK),

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