1*4882a593Smuzhiyun============================================== 2*4882a593Smuzhiyunspi_lm70llp : LM70-LLP parport-to-SPI adapter 3*4882a593Smuzhiyun============================================== 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunSupported board/chip: 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun * National Semiconductor LM70 LLP evaluation board 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun Datasheet: http://www.national.com/pf/LM/LM70.html 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunAuthor: 12*4882a593Smuzhiyun Kaiwan N Billimoria <kaiwan@designergraphix.com> 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunDescription 15*4882a593Smuzhiyun----------- 16*4882a593SmuzhiyunThis driver provides glue code connecting a National Semiconductor LM70 LLP 17*4882a593Smuzhiyuntemperature sensor evaluation board to the kernel's SPI core subsystem. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunThis is a SPI master controller driver. It can be used in conjunction with 20*4882a593Smuzhiyun(layered under) the LM70 logical driver (a "SPI protocol driver"). 21*4882a593SmuzhiyunIn effect, this driver turns the parallel port interface on the eval board 22*4882a593Smuzhiyuninto a SPI bus with a single device, which will be driven by the generic 23*4882a593SmuzhiyunLM70 driver (drivers/hwmon/lm70.c). 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunHardware Interfacing 27*4882a593Smuzhiyun-------------------- 28*4882a593SmuzhiyunThe schematic for this particular board (the LM70EVAL-LLP) is 29*4882a593Smuzhiyunavailable (on page 4) here: 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun http://www.national.com/appinfo/tempsensors/files/LM70LLPEVALmanual.pdf 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunThe hardware interfacing on the LM70 LLP eval board is as follows: 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun ======== == ========= ========== 36*4882a593Smuzhiyun Parallel LM70 LLP 37*4882a593Smuzhiyun Port . Direction JP2 Header 38*4882a593Smuzhiyun ======== == ========= ========== 39*4882a593Smuzhiyun D0 2 - - 40*4882a593Smuzhiyun D1 3 --> V+ 5 41*4882a593Smuzhiyun D2 4 --> V+ 5 42*4882a593Smuzhiyun D3 5 --> V+ 5 43*4882a593Smuzhiyun D4 6 --> V+ 5 44*4882a593Smuzhiyun D5 7 --> nCS 8 45*4882a593Smuzhiyun D6 8 --> SCLK 3 46*4882a593Smuzhiyun D7 9 --> SI/O 5 47*4882a593Smuzhiyun GND 25 - GND 7 48*4882a593Smuzhiyun Select 13 <-- SI/O 1 49*4882a593Smuzhiyun ======== == ========= ========== 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunNote that since the LM70 uses a "3-wire" variant of SPI, the SI/SO pin 52*4882a593Smuzhiyunis connected to both pin D7 (as Master Out) and Select (as Master In) 53*4882a593Smuzhiyunusing an arrangement that lets either the parport or the LM70 pull the 54*4882a593Smuzhiyunpin low. This can't be shared with true SPI devices, but other 3-wire 55*4882a593Smuzhiyundevices might share the same SI/SO pin. 56*4882a593Smuzhiyun 57*4882a593SmuzhiyunThe bitbanger routine in this driver (lm70_txrx) is called back from 58*4882a593Smuzhiyunthe bound "hwmon/lm70" protocol driver through its sysfs hook, using a 59*4882a593Smuzhiyunspi_write_then_read() call. It performs Mode 0 (SPI/Microwire) bitbanging. 60*4882a593SmuzhiyunThe lm70 driver then inteprets the resulting digital temperature value 61*4882a593Smuzhiyunand exports it through sysfs. 62*4882a593Smuzhiyun 63*4882a593SmuzhiyunA "gotcha": National Semiconductor's LM70 LLP eval board circuit schematic 64*4882a593Smuzhiyunshows that the SI/O line from the LM70 chip is connected to the base of a 65*4882a593Smuzhiyuntransistor Q1 (and also a pullup, and a zener diode to D7); while the 66*4882a593Smuzhiyuncollector is tied to VCC. 67*4882a593Smuzhiyun 68*4882a593SmuzhiyunInterpreting this circuit, when the LM70 SI/O line is High (or tristate 69*4882a593Smuzhiyunand not grounded by the host via D7), the transistor conducts and switches 70*4882a593Smuzhiyunthe collector to zero, which is reflected on pin 13 of the DB25 parport 71*4882a593Smuzhiyunconnector. When SI/O is Low (driven by the LM70 or the host) on the other 72*4882a593Smuzhiyunhand, the transistor is cut off and the voltage tied to it's collector is 73*4882a593Smuzhiyunreflected on pin 13 as a High level. 74*4882a593Smuzhiyun 75*4882a593SmuzhiyunSo: the getmiso inline routine in this driver takes this fact into account, 76*4882a593Smuzhiyuninverting the value read at pin 13. 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun 79*4882a593SmuzhiyunThanks to 80*4882a593Smuzhiyun--------- 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun- David Brownell for mentoring the SPI-side driver development. 83*4882a593Smuzhiyun- Dr.Craig Hollabaugh for the (early) "manual" bitbanging driver version. 84*4882a593Smuzhiyun- Nadir Billimoria for help interpreting the circuit schematic. 85