1*4882a593SmuzhiyunAnalog Devices AD2S90 Resolver-to-Digital Converter 2*4882a593Smuzhiyun 3*4882a593Smuzhiyunhttps://www.analog.com/en/products/ad2s90.html 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun - compatible: should be "adi,ad2s90" 7*4882a593Smuzhiyun - reg: SPI chip select number for the device 8*4882a593Smuzhiyun - spi-max-frequency: set maximum clock frequency, must be 830000 9*4882a593Smuzhiyun - spi-cpol and spi-cpha: 10*4882a593Smuzhiyun Either SPI mode (0,0) or (1,1) must be used, so specify none or both of 11*4882a593Smuzhiyun spi-cpha, spi-cpol. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunSee for more details: 14*4882a593Smuzhiyun Documentation/devicetree/bindings/spi/spi-bus.txt 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunNote about max frequency: 17*4882a593Smuzhiyun Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns 18*4882a593Smuzhiyun delay is expected between the application of a logic LO to CS and the 19*4882a593Smuzhiyun application of SCLK, as also specified. And since the delay is not 20*4882a593Smuzhiyun implemented in the spi code, to satisfy it, SCLK's period should be at most 21*4882a593Smuzhiyun 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives 22*4882a593Smuzhiyun roughly 830000Hz. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunExample: 25*4882a593Smuzhiyunresolver@0 { 26*4882a593Smuzhiyun compatible = "adi,ad2s90"; 27*4882a593Smuzhiyun reg = <0>; 28*4882a593Smuzhiyun spi-max-frequency = <830000>; 29*4882a593Smuzhiyun spi-cpol; 30*4882a593Smuzhiyun spi-cpha; 31*4882a593Smuzhiyun}; 32