1*4882a593SmuzhiyunPCM512x audio CODECs 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThese devices support both I2C and SPI (configured with pin strapping 4*4882a593Smuzhiyunon the board). 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun - compatible : One of "ti,pcm5121", "ti,pcm5122", "ti,pcm5141" or 9*4882a593Smuzhiyun "ti,pcm5142" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun - reg : the I2C address of the device for I2C, the chip select 12*4882a593Smuzhiyun number for SPI. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun - AVDD-supply, DVDD-supply, and CPVDD-supply : power supplies for the 15*4882a593Smuzhiyun device, as covered in bindings/regulator/regulator.txt 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunOptional properties: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun - clocks : A clock specifier for the clock connected as SCLK. If this 20*4882a593Smuzhiyun is absent the device will be configured to clock from BCLK. If pll-in 21*4882a593Smuzhiyun and pll-out are specified in addition to a clock, the device is 22*4882a593Smuzhiyun configured to accept clock input on a specified gpio pin. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun - pll-in, pll-out : gpio pins used to connect the pll using <1> 25*4882a593Smuzhiyun through <6>. The device will be configured for clock input on the 26*4882a593Smuzhiyun given pll-in pin and PLL output on the given pll-out pin. An 27*4882a593Smuzhiyun external connection from the pll-out pin to the SCLK pin is assumed. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunExamples: 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun pcm5122: pcm5122@4c { 32*4882a593Smuzhiyun compatible = "ti,pcm5122"; 33*4882a593Smuzhiyun reg = <0x4c>; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun AVDD-supply = <®_3v3_analog>; 36*4882a593Smuzhiyun DVDD-supply = <®_1v8>; 37*4882a593Smuzhiyun CPVDD-supply = <®_3v3>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun pcm5142: pcm5142@4c { 42*4882a593Smuzhiyun compatible = "ti,pcm5142"; 43*4882a593Smuzhiyun reg = <0x4c>; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun AVDD-supply = <®_3v3_analog>; 46*4882a593Smuzhiyun DVDD-supply = <®_1v8>; 47*4882a593Smuzhiyun CPVDD-supply = <®_3v3>; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun clocks = <&sck>; 50*4882a593Smuzhiyun pll-in = <3>; 51*4882a593Smuzhiyun pll-out = <6>; 52*4882a593Smuzhiyun }; 53