Searched refs:MX6QDL_PAD_EIM_A25__GPIO5_IO02 (Results 1 – 21 of 21) sorted by relevance
18 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x0f0b0 /* WL_RST_N */
121 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */
333 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
379 fsl,pins = <MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000>;
321 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* LED1 */
418 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
335 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1B0B0
75 #define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0 macro
486 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */
578 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */
329 #define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0 macro
539 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1
331 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /*LCD power*/
443 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */
600 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
432 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
380 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
1097 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
220 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
79 #define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0 macro
333 #define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0 macro