xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx6q-kp.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright 2018
4*4882a593Smuzhiyun * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include "imx6q.dtsi"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
12*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h>
13*4882a593Smuzhiyun#include <dt-bindings/sound/fsl-imx-audmux.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun/ {
16*4882a593Smuzhiyun	backlight_lcd: backlight-lcd {
17*4882a593Smuzhiyun		compatible = "pwm-backlight";
18*4882a593Smuzhiyun		pwms = <&pwm1 0 5000000>;
19*4882a593Smuzhiyun		brightness-levels = <0 255>;
20*4882a593Smuzhiyun		num-interpolated-steps = <255>;
21*4882a593Smuzhiyun		default-brightness-level = <250>;
22*4882a593Smuzhiyun	};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun	beeper {
25*4882a593Smuzhiyun		compatible = "pwm-beeper";
26*4882a593Smuzhiyun		pwms = <&pwm2 0 500000>;
27*4882a593Smuzhiyun	};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun	lcd_display: display {
30*4882a593Smuzhiyun		compatible = "fsl,imx-parallel-display";
31*4882a593Smuzhiyun		#address-cells = <1>;
32*4882a593Smuzhiyun		#size-cells = <0>;
33*4882a593Smuzhiyun		interface-pix-fmt = "rgb24";
34*4882a593Smuzhiyun		pinctrl-names = "default";
35*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_ipu1>;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun		port@0 {
38*4882a593Smuzhiyun			reg = <0>;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun			lcd_display_in: endpoint {
41*4882a593Smuzhiyun				remote-endpoint = <&ipu1_di0_disp0>;
42*4882a593Smuzhiyun			};
43*4882a593Smuzhiyun		};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun		port@1 {
46*4882a593Smuzhiyun			reg = <1>;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun			lcd_display_out: endpoint {
49*4882a593Smuzhiyun				remote-endpoint = <&lcd_panel_in>;
50*4882a593Smuzhiyun			};
51*4882a593Smuzhiyun		};
52*4882a593Smuzhiyun	};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun	lcd_panel: lcd-panel {
55*4882a593Smuzhiyun		compatible = "auo,g070vvn01";
56*4882a593Smuzhiyun		backlight = <&backlight_lcd>;
57*4882a593Smuzhiyun		power-supply = <&reg_display>;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun		port {
60*4882a593Smuzhiyun			lcd_panel_in: endpoint {
61*4882a593Smuzhiyun				remote-endpoint = <&lcd_display_out>;
62*4882a593Smuzhiyun			};
63*4882a593Smuzhiyun		};
64*4882a593Smuzhiyun	};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun	leds {
67*4882a593Smuzhiyun		compatible = "gpio-leds";
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun		green {
70*4882a593Smuzhiyun			label = "led1";
71*4882a593Smuzhiyun			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
72*4882a593Smuzhiyun			linux,default-trigger = "gpio";
73*4882a593Smuzhiyun			default-state = "off";
74*4882a593Smuzhiyun		};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun		red {
77*4882a593Smuzhiyun			label = "led0";
78*4882a593Smuzhiyun			gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
79*4882a593Smuzhiyun			linux,default-trigger = "gpio";
80*4882a593Smuzhiyun			default-state = "off";
81*4882a593Smuzhiyun		};
82*4882a593Smuzhiyun	};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun	reg_3p3v: regulator-3p3v {
85*4882a593Smuzhiyun		compatible = "regulator-fixed";
86*4882a593Smuzhiyun		regulator-name = "3P3V";
87*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
88*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
89*4882a593Smuzhiyun		regulator-always-on;
90*4882a593Smuzhiyun	};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun	reg_audio: regulator-audio {
93*4882a593Smuzhiyun		compatible = "regulator-fixed";
94*4882a593Smuzhiyun		regulator-name = "sgtl5000-supply";
95*4882a593Smuzhiyun		gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>;
96*4882a593Smuzhiyun		enable-active-high;
97*4882a593Smuzhiyun		regulator-always-on;
98*4882a593Smuzhiyun	};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun	reg_display: regulator-display {
101*4882a593Smuzhiyun		compatible = "regulator-fixed";
102*4882a593Smuzhiyun		regulator-name = "display-supply";
103*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
104*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
105*4882a593Smuzhiyun		regulator-always-on;
106*4882a593Smuzhiyun	};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun	reg_usb_h1_vbus: regulator-usb_h1_vbus {
109*4882a593Smuzhiyun		compatible = "regulator-fixed";
110*4882a593Smuzhiyun		regulator-name = "usb_h1_vbus";
111*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
112*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
113*4882a593Smuzhiyun		enable-active-high;
114*4882a593Smuzhiyun	};
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun	sound {
117*4882a593Smuzhiyun		compatible = "simple-audio-card";
118*4882a593Smuzhiyun		simple-audio-card,name = "imx6q-sgtl5000-audio";
119*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
120*4882a593Smuzhiyun		simple-audio-card,bitclock-master = <&codec_dai>;
121*4882a593Smuzhiyun		simple-audio-card,frame-master = <&codec_dai>;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun		cpu_dai: simple-audio-card,cpu {
124*4882a593Smuzhiyun			sound-dai = <&ssi1>;
125*4882a593Smuzhiyun		};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun		codec_dai: simple-audio-card,codec {
128*4882a593Smuzhiyun			sound-dai = <&sgtl5000>;
129*4882a593Smuzhiyun		};
130*4882a593Smuzhiyun	};
131*4882a593Smuzhiyun};
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun&audmux {
134*4882a593Smuzhiyun	pinctrl-names = "default";
135*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_audmux>;
136*4882a593Smuzhiyun	status = "okay";
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun	ssi1 {
139*4882a593Smuzhiyun		fsl,audmux-port = <0>;
140*4882a593Smuzhiyun		fsl,port-config = <
141*4882a593Smuzhiyun			(IMX_AUDMUX_V2_PTCR_SYN |
142*4882a593Smuzhiyun			IMX_AUDMUX_V2_PTCR_TFSEL(2) |
143*4882a593Smuzhiyun			IMX_AUDMUX_V2_PTCR_TCSEL(2) |
144*4882a593Smuzhiyun			IMX_AUDMUX_V2_PTCR_TFSDIR |
145*4882a593Smuzhiyun			IMX_AUDMUX_V2_PTCR_TCLKDIR)
146*4882a593Smuzhiyun			IMX_AUDMUX_V2_PDCR_RXDSEL(2)
147*4882a593Smuzhiyun		>;
148*4882a593Smuzhiyun	};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun	aud3 {
151*4882a593Smuzhiyun		fsl,audmux-port = <2>;
152*4882a593Smuzhiyun		fsl,port-config = <
153*4882a593Smuzhiyun			IMX_AUDMUX_V2_PTCR_SYN
154*4882a593Smuzhiyun			IMX_AUDMUX_V2_PDCR_RXDSEL(0)
155*4882a593Smuzhiyun		>;
156*4882a593Smuzhiyun	};
157*4882a593Smuzhiyun};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun&can1 {
160*4882a593Smuzhiyun	pinctrl-names = "default";
161*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan1>;
162*4882a593Smuzhiyun};
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun&can2 {
165*4882a593Smuzhiyun	pinctrl-names = "default";
166*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan2>;
167*4882a593Smuzhiyun};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun&fec {
170*4882a593Smuzhiyun	pinctrl-names = "default";
171*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet>;
172*4882a593Smuzhiyun	phy-mode = "rgmii";
173*4882a593Smuzhiyun	fsl,magic-packet;
174*4882a593Smuzhiyun	status = "okay";
175*4882a593Smuzhiyun};
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun&i2c1 {
178*4882a593Smuzhiyun	clock-frequency = <400000>;
179*4882a593Smuzhiyun	pinctrl-names = "default";
180*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
181*4882a593Smuzhiyun	status = "okay";
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun	touchscreen@5d {
184*4882a593Smuzhiyun		compatible = "goodix,gt911";
185*4882a593Smuzhiyun		reg = <0x5d>;
186*4882a593Smuzhiyun		pinctrl-names = "default";
187*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_ts>;
188*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
189*4882a593Smuzhiyun		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
190*4882a593Smuzhiyun		irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
191*4882a593Smuzhiyun		reset-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
192*4882a593Smuzhiyun	};
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun	ds1307: rtc@32 {
195*4882a593Smuzhiyun		compatible = "dallas,ds1307";
196*4882a593Smuzhiyun		reg = <0x32>;
197*4882a593Smuzhiyun	};
198*4882a593Smuzhiyun};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun&i2c2 {
201*4882a593Smuzhiyun	clock-frequency = <400000>;
202*4882a593Smuzhiyun	pinctrl-names = "default";
203*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
204*4882a593Smuzhiyun	status = "okay";
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun	sgtl5000: audio-codec@a {
207*4882a593Smuzhiyun		compatible = "fsl,sgtl5000";
208*4882a593Smuzhiyun		#sound-dai-cells = <0>;
209*4882a593Smuzhiyun		reg = <0x0a>;
210*4882a593Smuzhiyun		pinctrl-names = "default";
211*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_codec>;
212*4882a593Smuzhiyun		clocks = <&clks IMX6QDL_CLK_CKO>;
213*4882a593Smuzhiyun		VDDA-supply = <&reg_3p3v>;
214*4882a593Smuzhiyun		VDDIO-supply = <&reg_3p3v>;
215*4882a593Smuzhiyun	};
216*4882a593Smuzhiyun};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun&iomuxc {
219*4882a593Smuzhiyun	pinctrl_audmux: audmuxgrp {
220*4882a593Smuzhiyun		fsl,pins = <
221*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
222*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
223*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
224*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS	0x130b0
225*4882a593Smuzhiyun		>;
226*4882a593Smuzhiyun	};
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun	pinctrl_codec: codecgrp {
229*4882a593Smuzhiyun		fsl,pins = <
230*4882a593Smuzhiyun			MX6QDL_PAD_EIM_BCLK__GPIO6_IO31   0x1b0b0
231*4882a593Smuzhiyun			/* sgtl5000 sys_mclk clock routed to CLKO1 */
232*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_0__CCM_CLKO1      0x000b0
233*4882a593Smuzhiyun		>;
234*4882a593Smuzhiyun	};
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun	pinctrl_enet: enetgrp {
237*4882a593Smuzhiyun		fsl,pins = <
238*4882a593Smuzhiyun			MX6QDL_PAD_ENET_MDIO__ENET_MDIO	0x1b0b0
239*4882a593Smuzhiyun			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
240*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TXC__RGMII_TXC	0x1b0b0
241*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD0__RGMII_TD0	0x1b0b0
242*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD1__RGMII_TD1	0x1b0b0
243*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD2__RGMII_TD2	0x1b0b0
244*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD3__RGMII_TD3	0x1b0b0
245*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
246*4882a593Smuzhiyun			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
247*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RXC__RGMII_RXC	0x1b0b0
248*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD0__RGMII_RD0	0x1b0b0
249*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD1__RGMII_RD1	0x1b0b0
250*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD2__RGMII_RD2	0x1b0b0
251*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD3__RGMII_RD3	0x1b0b0
252*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
253*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
254*4882a593Smuzhiyun		>;
255*4882a593Smuzhiyun	};
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun	pinctrl_flexcan1: can1grp {
258*4882a593Smuzhiyun		fsl,pins = <
259*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_7__FLEXCAN1_TX        0x1b0b0
260*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX        0x1b0b0
261*4882a593Smuzhiyun		>;
262*4882a593Smuzhiyun	};
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun	pinctrl_flexcan2: can2grp {
265*4882a593Smuzhiyun		fsl,pins = <
266*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
267*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
268*4882a593Smuzhiyun		>;
269*4882a593Smuzhiyun	};
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun	pinctrl_i2c1: i2c1grp {
272*4882a593Smuzhiyun		fsl,pins = <
273*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA	0x4001b8b1
274*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL	0x4001b8b1
275*4882a593Smuzhiyun		>;
276*4882a593Smuzhiyun	};
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun	pinctrl_i2c2: i2c2grp {
279*4882a593Smuzhiyun		fsl,pins = <
280*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL3__I2C2_SCL	0x4001b8b1
281*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW3__I2C2_SDA	0x4001b8b1
282*4882a593Smuzhiyun		 >;
283*4882a593Smuzhiyun	};
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun	pinctrl_ipu1: ipu1grp {
286*4882a593Smuzhiyun		fsl,pins = <
287*4882a593Smuzhiyun			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
288*4882a593Smuzhiyun			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
289*4882a593Smuzhiyun			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
290*4882a593Smuzhiyun			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
291*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
292*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
293*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
294*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
295*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
296*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
297*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
298*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
299*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
300*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
301*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
302*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
303*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
304*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
305*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
306*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
307*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
308*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
309*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
310*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
311*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
312*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
313*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
314*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
315*4882a593Smuzhiyun		>;
316*4882a593Smuzhiyun	};
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun	pinctrl_pwm1: pwm1grp {
319*4882a593Smuzhiyun		fsl,pins = <
320*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT3__PWM1_OUT		0x1b0b1
321*4882a593Smuzhiyun		>;
322*4882a593Smuzhiyun	};
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun	pinctrl_pwm2: pwm2grp {
325*4882a593Smuzhiyun		fsl,pins = <
326*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
327*4882a593Smuzhiyun		>;
328*4882a593Smuzhiyun	};
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun	pinctrl_ts: tsgrp {
331*4882a593Smuzhiyun		fsl,pins = <
332*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
333*4882a593Smuzhiyun			MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
334*4882a593Smuzhiyun		>;
335*4882a593Smuzhiyun	};
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun	pinctrl_uart1: uart1grp {
338*4882a593Smuzhiyun		fsl,pins = <
339*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
340*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
341*4882a593Smuzhiyun		>;
342*4882a593Smuzhiyun	};
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun	pinctrl_uart2: uart2grp {
345*4882a593Smuzhiyun		fsl,pins = <
346*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
347*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
348*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D28__UART2_CTS_B         0x1b0b1
349*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D29__UART2_RTS_B         0x1b0b1
350*4882a593Smuzhiyun		>;
351*4882a593Smuzhiyun	};
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun	pinctrl_usdhc2: usdhc2grp {
354*4882a593Smuzhiyun		fsl,pins = <
355*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
356*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
357*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
358*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
359*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
360*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
361*4882a593Smuzhiyun		>;
362*4882a593Smuzhiyun	};
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun	pinctrl_usdhc4: usdhc4grp {
365*4882a593Smuzhiyun		fsl,pins = <
366*4882a593Smuzhiyun			MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
367*4882a593Smuzhiyun			MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
368*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
369*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
370*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
371*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
372*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059
373*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059
374*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059
375*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
376*4882a593Smuzhiyun		>;
377*4882a593Smuzhiyun	};
378*4882a593Smuzhiyun};
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun&pwm1 {
381*4882a593Smuzhiyun	#pwm-cells = <2>;
382*4882a593Smuzhiyun	pinctrl-names = "default";
383*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm1>;
384*4882a593Smuzhiyun	status = "okay";
385*4882a593Smuzhiyun};
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun&pwm2 {
388*4882a593Smuzhiyun	#pwm-cells = <2>;
389*4882a593Smuzhiyun	pinctrl-names = "default";
390*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm2>;
391*4882a593Smuzhiyun	status = "okay";
392*4882a593Smuzhiyun};
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun&ssi1 {
395*4882a593Smuzhiyun	status = "okay";
396*4882a593Smuzhiyun};
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun&uart1 {
399*4882a593Smuzhiyun	pinctrl-names = "default";
400*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
401*4882a593Smuzhiyun	status = "okay";
402*4882a593Smuzhiyun};
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun&uart2 {
405*4882a593Smuzhiyun	pinctrl-names = "default";
406*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
407*4882a593Smuzhiyun	uart-has-rtscts;
408*4882a593Smuzhiyun};
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun&usbh1 {
411*4882a593Smuzhiyun	status = "okay";
412*4882a593Smuzhiyun};
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun&usdhc2 {
415*4882a593Smuzhiyun	pinctrl-names = "default";
416*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
417*4882a593Smuzhiyun	bus-width = <4>;
418*4882a593Smuzhiyun	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
419*4882a593Smuzhiyun	status = "okay";
420*4882a593Smuzhiyun};
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun&usdhc4 {
423*4882a593Smuzhiyun	pinctrl-names = "default";
424*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc4>;
425*4882a593Smuzhiyun	bus-width = <8>;
426*4882a593Smuzhiyun	non-removable;
427*4882a593Smuzhiyun	no-1-8-v;
428*4882a593Smuzhiyun	keep-power-in-suspend;
429*4882a593Smuzhiyun	status = "okay";
430*4882a593Smuzhiyun};
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun&wdog1 {
433*4882a593Smuzhiyun	status = "okay";
434*4882a593Smuzhiyun};
435