1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2013 Data Modul AG 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 9*4882a593Smuzhiyun#include "imx6q.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "Data Modul eDM-QMX6 Board"; 13*4882a593Smuzhiyun compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun chosen { 16*4882a593Smuzhiyun stdout-path = &uart2; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun aliases { 20*4882a593Smuzhiyun gpio7 = &stmpe_gpio1; 21*4882a593Smuzhiyun gpio8 = &stmpe_gpio2; 22*4882a593Smuzhiyun stmpe-i2c0 = &stmpe1; 23*4882a593Smuzhiyun stmpe-i2c1 = &stmpe2; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun memory@10000000 { 27*4882a593Smuzhiyun device_type = "memory"; 28*4882a593Smuzhiyun reg = <0x10000000 0x80000000>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun regulators { 32*4882a593Smuzhiyun compatible = "simple-bus"; 33*4882a593Smuzhiyun #address-cells = <1>; 34*4882a593Smuzhiyun #size-cells = <0>; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun reg_3p3v: regulator@0 { 37*4882a593Smuzhiyun compatible = "regulator-fixed"; 38*4882a593Smuzhiyun reg = <0>; 39*4882a593Smuzhiyun regulator-name = "3P3V"; 40*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 41*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 42*4882a593Smuzhiyun regulator-always-on; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun reg_usb_otg_switch: regulator@1 { 46*4882a593Smuzhiyun compatible = "regulator-fixed"; 47*4882a593Smuzhiyun reg = <1>; 48*4882a593Smuzhiyun regulator-name = "usb_otg_switch"; 49*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 50*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 51*4882a593Smuzhiyun gpio = <&gpio7 12 0>; 52*4882a593Smuzhiyun regulator-boot-on; 53*4882a593Smuzhiyun regulator-always-on; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun reg_usb_host1: regulator@2 { 57*4882a593Smuzhiyun compatible = "regulator-fixed"; 58*4882a593Smuzhiyun reg = <2>; 59*4882a593Smuzhiyun regulator-name = "usb_host1_en"; 60*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 61*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 62*4882a593Smuzhiyun gpio = <&gpio3 31 0>; 63*4882a593Smuzhiyun enable-active-high; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun gpio-leds { 68*4882a593Smuzhiyun compatible = "gpio-leds"; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun led-blue { 71*4882a593Smuzhiyun label = "blue"; 72*4882a593Smuzhiyun gpios = <&stmpe_gpio1 8 GPIO_ACTIVE_HIGH>; 73*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun led-green { 77*4882a593Smuzhiyun label = "green"; 78*4882a593Smuzhiyun gpios = <&stmpe_gpio1 9 GPIO_ACTIVE_HIGH>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun led-pink { 82*4882a593Smuzhiyun label = "pink"; 83*4882a593Smuzhiyun gpios = <&stmpe_gpio1 10 GPIO_ACTIVE_HIGH>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun led-red { 87*4882a593Smuzhiyun label = "red"; 88*4882a593Smuzhiyun gpios = <&stmpe_gpio1 11 GPIO_ACTIVE_HIGH>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun}; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun&can1 { 94*4882a593Smuzhiyun pinctrl-names = "default"; 95*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_can1>; 96*4882a593Smuzhiyun status = "okay"; 97*4882a593Smuzhiyun}; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun&ecspi5 { 100*4882a593Smuzhiyun pinctrl-names = "default"; 101*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ecspi5>; 102*4882a593Smuzhiyun cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 103*4882a593Smuzhiyun status = "okay"; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun flash: flash@0 { 106*4882a593Smuzhiyun compatible = "m25p80", "jedec,spi-nor"; 107*4882a593Smuzhiyun spi-max-frequency = <40000000>; 108*4882a593Smuzhiyun reg = <0>; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun}; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun&fec { 113*4882a593Smuzhiyun pinctrl-names = "default"; 114*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet>; 115*4882a593Smuzhiyun phy-mode = "rgmii"; 116*4882a593Smuzhiyun phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 117*4882a593Smuzhiyun phy-supply = <&vgen2_1v2_eth>; 118*4882a593Smuzhiyun status = "okay"; 119*4882a593Smuzhiyun}; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun&i2c1 { 122*4882a593Smuzhiyun clock-frequency = <100000>; 123*4882a593Smuzhiyun pinctrl-names = "default"; 124*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 125*4882a593Smuzhiyun status = "okay"; 126*4882a593Smuzhiyun}; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun&i2c2 { 129*4882a593Smuzhiyun clock-frequency = <100000>; 130*4882a593Smuzhiyun pinctrl-names = "default"; 131*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2 132*4882a593Smuzhiyun &pinctrl_stmpe1 133*4882a593Smuzhiyun &pinctrl_stmpe2 134*4882a593Smuzhiyun &pinctrl_pfuze>; 135*4882a593Smuzhiyun status = "okay"; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun pmic: pfuze100@8 { 138*4882a593Smuzhiyun compatible = "fsl,pfuze100"; 139*4882a593Smuzhiyun reg = <0x08>; 140*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 141*4882a593Smuzhiyun interrupts = <20 8>; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun regulators { 144*4882a593Smuzhiyun sw1a_reg: sw1ab { 145*4882a593Smuzhiyun regulator-min-microvolt = <300000>; 146*4882a593Smuzhiyun regulator-max-microvolt = <1875000>; 147*4882a593Smuzhiyun regulator-boot-on; 148*4882a593Smuzhiyun regulator-always-on; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun sw1c_reg: sw1c { 152*4882a593Smuzhiyun regulator-min-microvolt = <300000>; 153*4882a593Smuzhiyun regulator-max-microvolt = <1875000>; 154*4882a593Smuzhiyun regulator-boot-on; 155*4882a593Smuzhiyun regulator-always-on; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun sw2_reg: sw2 { 159*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 160*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 161*4882a593Smuzhiyun regulator-boot-on; 162*4882a593Smuzhiyun regulator-always-on; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun sw3a_reg: sw3a { 166*4882a593Smuzhiyun regulator-min-microvolt = <400000>; 167*4882a593Smuzhiyun regulator-max-microvolt = <1975000>; 168*4882a593Smuzhiyun regulator-boot-on; 169*4882a593Smuzhiyun regulator-always-on; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun sw3b_reg: sw3b { 173*4882a593Smuzhiyun regulator-min-microvolt = <400000>; 174*4882a593Smuzhiyun regulator-max-microvolt = <1975000>; 175*4882a593Smuzhiyun regulator-boot-on; 176*4882a593Smuzhiyun regulator-always-on; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun sw4_reg: sw4 { 180*4882a593Smuzhiyun regulator-min-microvolt = <400000>; 181*4882a593Smuzhiyun regulator-max-microvolt = <1975000>; 182*4882a593Smuzhiyun regulator-always-on; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun swbst_reg: swbst { 186*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 187*4882a593Smuzhiyun regulator-max-microvolt = <5150000>; 188*4882a593Smuzhiyun regulator-always-on; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun snvs_reg: vsnvs { 192*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 193*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 194*4882a593Smuzhiyun regulator-boot-on; 195*4882a593Smuzhiyun regulator-always-on; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun vref_reg: vrefddr { 199*4882a593Smuzhiyun regulator-boot-on; 200*4882a593Smuzhiyun regulator-always-on; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun vgen1_reg: vgen1 { 204*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 205*4882a593Smuzhiyun regulator-max-microvolt = <1550000>; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun vgen2_1v2_eth: vgen2 { 209*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 210*4882a593Smuzhiyun regulator-max-microvolt = <1550000>; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun vdd_high_in: vgen3 { 214*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 215*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 216*4882a593Smuzhiyun regulator-boot-on; 217*4882a593Smuzhiyun regulator-always-on; 218*4882a593Smuzhiyun }; 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun vgen4_reg: vgen4 { 221*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 222*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 223*4882a593Smuzhiyun regulator-always-on; 224*4882a593Smuzhiyun }; 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun vgen5_reg: vgen5 { 227*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 228*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 229*4882a593Smuzhiyun regulator-always-on; 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun vgen6_reg: vgen6 { 233*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 234*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 235*4882a593Smuzhiyun regulator-always-on; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun }; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun stmpe1: stmpe1601@40 { 241*4882a593Smuzhiyun compatible = "st,stmpe1601"; 242*4882a593Smuzhiyun reg = <0x40>; 243*4882a593Smuzhiyun interrupts = <30 0>; 244*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 245*4882a593Smuzhiyun vcc-supply = <&sw2_reg>; 246*4882a593Smuzhiyun vio-supply = <&sw2_reg>; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun stmpe_gpio1: stmpe_gpio { 249*4882a593Smuzhiyun #gpio-cells = <2>; 250*4882a593Smuzhiyun compatible = "st,stmpe-gpio"; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun }; 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun stmpe2: stmpe1601@44 { 255*4882a593Smuzhiyun compatible = "st,stmpe1601"; 256*4882a593Smuzhiyun reg = <0x44>; 257*4882a593Smuzhiyun interrupts = <2 0>; 258*4882a593Smuzhiyun interrupt-parent = <&gpio5>; 259*4882a593Smuzhiyun vcc-supply = <&sw2_reg>; 260*4882a593Smuzhiyun vio-supply = <&sw2_reg>; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun stmpe_gpio2: stmpe_gpio { 263*4882a593Smuzhiyun #gpio-cells = <2>; 264*4882a593Smuzhiyun compatible = "st,stmpe-gpio"; 265*4882a593Smuzhiyun }; 266*4882a593Smuzhiyun }; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun temp1: ad7414@4c { 269*4882a593Smuzhiyun compatible = "ad,ad7414"; 270*4882a593Smuzhiyun reg = <0x4c>; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun temp2: ad7414@4d { 274*4882a593Smuzhiyun compatible = "ad,ad7414"; 275*4882a593Smuzhiyun reg = <0x4d>; 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun rtc: m41t62@68 { 279*4882a593Smuzhiyun compatible = "st,m41t62"; 280*4882a593Smuzhiyun reg = <0x68>; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun}; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun&i2c3 { 285*4882a593Smuzhiyun clock-frequency = <100000>; 286*4882a593Smuzhiyun pinctrl-names = "default"; 287*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 288*4882a593Smuzhiyun status = "okay"; 289*4882a593Smuzhiyun}; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun&iomuxc { 292*4882a593Smuzhiyun pinctrl-names = "default"; 293*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_hog>; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun imx6q-dmo-edmqmx6 { 296*4882a593Smuzhiyun pinctrl_hog: hoggrp { 297*4882a593Smuzhiyun fsl,pins = < 298*4882a593Smuzhiyun MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000 299*4882a593Smuzhiyun MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000 300*4882a593Smuzhiyun >; 301*4882a593Smuzhiyun }; 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun pinctrl_can1: can1grp { 304*4882a593Smuzhiyun fsl,pins = < 305*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 306*4882a593Smuzhiyun MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 307*4882a593Smuzhiyun >; 308*4882a593Smuzhiyun }; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun pinctrl_ecspi5: ecspi5rp-1 { 311*4882a593Smuzhiyun fsl,pins = < 312*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000 313*4882a593Smuzhiyun MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000 314*4882a593Smuzhiyun MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000 315*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x80000000 316*4882a593Smuzhiyun >; 317*4882a593Smuzhiyun }; 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun pinctrl_enet: enetgrp { 320*4882a593Smuzhiyun fsl,pins = < 321*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 322*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 323*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 324*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 325*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 326*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 327*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 328*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 329*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 330*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 331*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 332*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 333*4882a593Smuzhiyun MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 334*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 335*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 336*4882a593Smuzhiyun MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 337*4882a593Smuzhiyun MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 338*4882a593Smuzhiyun >; 339*4882a593Smuzhiyun }; 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 342*4882a593Smuzhiyun fsl,pins = < 343*4882a593Smuzhiyun MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 344*4882a593Smuzhiyun MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 345*4882a593Smuzhiyun >; 346*4882a593Smuzhiyun }; 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 349*4882a593Smuzhiyun fsl,pins = < 350*4882a593Smuzhiyun MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 351*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 352*4882a593Smuzhiyun >; 353*4882a593Smuzhiyun }; 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 356*4882a593Smuzhiyun fsl,pins = < 357*4882a593Smuzhiyun MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 358*4882a593Smuzhiyun MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 359*4882a593Smuzhiyun >; 360*4882a593Smuzhiyun }; 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun pinctrl_pcie: pciegrp { 363*4882a593Smuzhiyun fsl,pins = < 364*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x100b1 365*4882a593Smuzhiyun >; 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun pinctrl_pfuze: pfuze100grp1 { 369*4882a593Smuzhiyun fsl,pins = < 370*4882a593Smuzhiyun MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000 371*4882a593Smuzhiyun >; 372*4882a593Smuzhiyun }; 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun pinctrl_stmpe1: stmpe1grp { 375*4882a593Smuzhiyun fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>; 376*4882a593Smuzhiyun }; 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun pinctrl_stmpe2: stmpe2grp { 379*4882a593Smuzhiyun fsl,pins = <MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000>; 380*4882a593Smuzhiyun }; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 383*4882a593Smuzhiyun fsl,pins = < 384*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 385*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 386*4882a593Smuzhiyun >; 387*4882a593Smuzhiyun }; 388*4882a593Smuzhiyun 389*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 390*4882a593Smuzhiyun fsl,pins = < 391*4882a593Smuzhiyun MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 392*4882a593Smuzhiyun MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 393*4882a593Smuzhiyun >; 394*4882a593Smuzhiyun }; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun pinctrl_usbotg: usbotggrp { 397*4882a593Smuzhiyun fsl,pins = < 398*4882a593Smuzhiyun MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 399*4882a593Smuzhiyun >; 400*4882a593Smuzhiyun }; 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun pinctrl_usdhc3: usdhc3grp { 403*4882a593Smuzhiyun fsl,pins = < 404*4882a593Smuzhiyun MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 405*4882a593Smuzhiyun MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 406*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 407*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 408*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 409*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 410*4882a593Smuzhiyun >; 411*4882a593Smuzhiyun }; 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun pinctrl_usdhc4: usdhc4grp { 414*4882a593Smuzhiyun fsl,pins = < 415*4882a593Smuzhiyun MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 416*4882a593Smuzhiyun MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 417*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 418*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 419*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 420*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 421*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 422*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 423*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 424*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 425*4882a593Smuzhiyun >; 426*4882a593Smuzhiyun }; 427*4882a593Smuzhiyun }; 428*4882a593Smuzhiyun}; 429*4882a593Smuzhiyun 430*4882a593Smuzhiyun&pcie { 431*4882a593Smuzhiyun pinctrl-names = "default"; 432*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pcie>; 433*4882a593Smuzhiyun reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; 434*4882a593Smuzhiyun status = "okay"; 435*4882a593Smuzhiyun}; 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun&sata { 438*4882a593Smuzhiyun status = "okay"; 439*4882a593Smuzhiyun}; 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun&uart1 { 442*4882a593Smuzhiyun pinctrl-names = "default"; 443*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 444*4882a593Smuzhiyun status = "okay"; 445*4882a593Smuzhiyun}; 446*4882a593Smuzhiyun 447*4882a593Smuzhiyun&uart2 { 448*4882a593Smuzhiyun pinctrl-names = "default"; 449*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 450*4882a593Smuzhiyun status = "okay"; 451*4882a593Smuzhiyun}; 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun&usbh1 { 454*4882a593Smuzhiyun vbus-supply = <®_usb_host1>; 455*4882a593Smuzhiyun disable-over-current; 456*4882a593Smuzhiyun dr_mode = "host"; 457*4882a593Smuzhiyun status = "okay"; 458*4882a593Smuzhiyun}; 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun&usbotg { 461*4882a593Smuzhiyun pinctrl-names = "default"; 462*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotg>; 463*4882a593Smuzhiyun disable-over-current; 464*4882a593Smuzhiyun status = "okay"; 465*4882a593Smuzhiyun}; 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun&usdhc3 { 468*4882a593Smuzhiyun pinctrl-names = "default"; 469*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3>; 470*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 471*4882a593Smuzhiyun status = "okay"; 472*4882a593Smuzhiyun}; 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun&usdhc4 { 475*4882a593Smuzhiyun pinctrl-names = "default"; 476*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc4>; 477*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 478*4882a593Smuzhiyun non-removable; 479*4882a593Smuzhiyun bus-width = <8>; 480*4882a593Smuzhiyun status = "okay"; 481*4882a593Smuzhiyun}; 482