xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx6q-dhcom-som.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (C) 2015 DH electronics GmbH
4*4882a593Smuzhiyun * Copyright (C) 2018 Marek Vasut <marex@denx.de>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include "imx6q.dtsi"
8*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h>
9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
10*4882a593Smuzhiyun#include <dt-bindings/clock/imx6qdl-clock.h>
11*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun/ {
14*4882a593Smuzhiyun	aliases {
15*4882a593Smuzhiyun		mmc0 = &usdhc2;
16*4882a593Smuzhiyun		mmc1 = &usdhc3;
17*4882a593Smuzhiyun		mmc2 = &usdhc4;
18*4882a593Smuzhiyun		mmc3 = &usdhc1;
19*4882a593Smuzhiyun	};
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	memory@10000000 {
22*4882a593Smuzhiyun		device_type = "memory";
23*4882a593Smuzhiyun		reg = <0x10000000 0x40000000>;
24*4882a593Smuzhiyun	};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	reg_usb_otg_vbus: regulator-usb-otg-vbus {
27*4882a593Smuzhiyun		compatible = "regulator-fixed";
28*4882a593Smuzhiyun		regulator-name = "usb_otg_vbus";
29*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
30*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
31*4882a593Smuzhiyun	};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun	reg_usb_h1_vbus: regulator-usb-h1-vbus {
34*4882a593Smuzhiyun		compatible = "regulator-fixed";
35*4882a593Smuzhiyun		regulator-name = "usb_h1_vbus";
36*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
37*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
38*4882a593Smuzhiyun		gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
39*4882a593Smuzhiyun		enable-active-high;
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	reg_3p3v: regulator-3P3V {
43*4882a593Smuzhiyun		compatible = "regulator-fixed";
44*4882a593Smuzhiyun		regulator-name = "3P3V";
45*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
46*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
47*4882a593Smuzhiyun		regulator-always-on;
48*4882a593Smuzhiyun	};
49*4882a593Smuzhiyun};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun&can1 {
52*4882a593Smuzhiyun	pinctrl-names = "default";
53*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan1>;
54*4882a593Smuzhiyun};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun&can2 {
57*4882a593Smuzhiyun	pinctrl-names = "default";
58*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan2>;
59*4882a593Smuzhiyun};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun&ecspi1 {
62*4882a593Smuzhiyun	cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>;
63*4882a593Smuzhiyun	pinctrl-names = "default";
64*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
65*4882a593Smuzhiyun	status = "okay";
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun	flash@0 {	/* S25FL116K */
68*4882a593Smuzhiyun		#address-cells = <1>;
69*4882a593Smuzhiyun		#size-cells = <1>;
70*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
71*4882a593Smuzhiyun		spi-max-frequency = <50000000>;
72*4882a593Smuzhiyun		reg = <0>;
73*4882a593Smuzhiyun		m25p,fast-read;
74*4882a593Smuzhiyun	};
75*4882a593Smuzhiyun};
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun&ecspi2 {
78*4882a593Smuzhiyun	cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
79*4882a593Smuzhiyun	pinctrl-names = "default";
80*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi2>;
81*4882a593Smuzhiyun	status = "okay";
82*4882a593Smuzhiyun};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun&fec {
85*4882a593Smuzhiyun	pinctrl-names = "default";
86*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet_100M>;
87*4882a593Smuzhiyun	phy-mode = "rmii";
88*4882a593Smuzhiyun	phy-handle = <&ethphy0>;
89*4882a593Smuzhiyun	status = "okay";
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun	mdio {
92*4882a593Smuzhiyun		#address-cells = <1>;
93*4882a593Smuzhiyun		#size-cells = <0>;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun		ethphy0: ethernet-phy@0 {	/* SMSC LAN8710Ai */
96*4882a593Smuzhiyun			reg = <0>;
97*4882a593Smuzhiyun			max-speed = <100>;
98*4882a593Smuzhiyun			reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
99*4882a593Smuzhiyun			reset-assert-us = <1000>;
100*4882a593Smuzhiyun			reset-deassert-us = <1000>;
101*4882a593Smuzhiyun			smsc,disable-energy-detect; /* Make plugin detection reliable */
102*4882a593Smuzhiyun		};
103*4882a593Smuzhiyun	};
104*4882a593Smuzhiyun};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun&i2c1 {
107*4882a593Smuzhiyun	clock-frequency = <100000>;
108*4882a593Smuzhiyun	pinctrl-names = "default", "gpio";
109*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
110*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_i2c1_gpio>;
111*4882a593Smuzhiyun	scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
112*4882a593Smuzhiyun	sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
113*4882a593Smuzhiyun	status = "okay";
114*4882a593Smuzhiyun};
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun&i2c2 {
117*4882a593Smuzhiyun	clock-frequency = <100000>;
118*4882a593Smuzhiyun	pinctrl-names = "default", "gpio";
119*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
120*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_i2c2_gpio>;
121*4882a593Smuzhiyun	scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
122*4882a593Smuzhiyun	sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
123*4882a593Smuzhiyun	status = "okay";
124*4882a593Smuzhiyun};
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun&i2c3 {
127*4882a593Smuzhiyun	clock-frequency = <100000>;
128*4882a593Smuzhiyun	pinctrl-names = "default", "gpio";
129*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c3>;
130*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_i2c3_gpio>;
131*4882a593Smuzhiyun	scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
132*4882a593Smuzhiyun	sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
133*4882a593Smuzhiyun	status = "okay";
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun	ltc3676: pmic@3c {
136*4882a593Smuzhiyun		compatible = "lltc,ltc3676";
137*4882a593Smuzhiyun		pinctrl-names = "default";
138*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_pmic_hw300>;
139*4882a593Smuzhiyun		reg = <0x3c>;
140*4882a593Smuzhiyun		interrupt-parent = <&gpio5>;
141*4882a593Smuzhiyun		interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun		regulators {
144*4882a593Smuzhiyun			sw1_reg: sw1 {
145*4882a593Smuzhiyun				regulator-min-microvolt = <787500>;
146*4882a593Smuzhiyun				regulator-max-microvolt = <1527272>;
147*4882a593Smuzhiyun				lltc,fb-voltage-divider = <100000 110000>;
148*4882a593Smuzhiyun				regulator-suspend-mem-microvolt = <1040000>;
149*4882a593Smuzhiyun				regulator-ramp-delay = <7000>;
150*4882a593Smuzhiyun				regulator-boot-on;
151*4882a593Smuzhiyun				regulator-always-on;
152*4882a593Smuzhiyun			};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun			sw2_reg: sw2 {
155*4882a593Smuzhiyun				regulator-min-microvolt = <1885714>;
156*4882a593Smuzhiyun				regulator-max-microvolt = <3657142>;
157*4882a593Smuzhiyun				lltc,fb-voltage-divider = <100000 28000>;
158*4882a593Smuzhiyun				regulator-ramp-delay = <7000>;
159*4882a593Smuzhiyun				regulator-boot-on;
160*4882a593Smuzhiyun				regulator-always-on;
161*4882a593Smuzhiyun			};
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun			sw3_reg: sw3 {
164*4882a593Smuzhiyun				regulator-min-microvolt = <787500>;
165*4882a593Smuzhiyun				regulator-max-microvolt = <1527272>;
166*4882a593Smuzhiyun				lltc,fb-voltage-divider = <100000 110000>;
167*4882a593Smuzhiyun				regulator-suspend-mem-microvolt = <980000>;
168*4882a593Smuzhiyun				regulator-ramp-delay = <7000>;
169*4882a593Smuzhiyun				regulator-boot-on;
170*4882a593Smuzhiyun				regulator-always-on;
171*4882a593Smuzhiyun			};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun			sw4_reg: sw4 {
174*4882a593Smuzhiyun				regulator-min-microvolt = <855571>;
175*4882a593Smuzhiyun				regulator-max-microvolt = <1659291>;
176*4882a593Smuzhiyun				lltc,fb-voltage-divider = <100000 93100>;
177*4882a593Smuzhiyun				regulator-ramp-delay = <7000>;
178*4882a593Smuzhiyun				regulator-boot-on;
179*4882a593Smuzhiyun				regulator-always-on;
180*4882a593Smuzhiyun			};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun			ldo1_reg: ldo1 {
183*4882a593Smuzhiyun				regulator-min-microvolt = <3240306>;
184*4882a593Smuzhiyun				regulator-max-microvolt = <3240306>;
185*4882a593Smuzhiyun				lltc,fb-voltage-divider = <102000 29400>;
186*4882a593Smuzhiyun				regulator-boot-on;
187*4882a593Smuzhiyun				regulator-always-on;
188*4882a593Smuzhiyun			};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun			ldo2_reg: ldo2 {
191*4882a593Smuzhiyun				regulator-min-microvolt = <2484708>;
192*4882a593Smuzhiyun				regulator-max-microvolt = <2484708>;
193*4882a593Smuzhiyun				lltc,fb-voltage-divider = <100000 41200>;
194*4882a593Smuzhiyun				regulator-boot-on;
195*4882a593Smuzhiyun				regulator-always-on;
196*4882a593Smuzhiyun			};
197*4882a593Smuzhiyun		};
198*4882a593Smuzhiyun	};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun	touchscreen@49 {	/* TSC2004 */
201*4882a593Smuzhiyun		compatible = "ti,tsc2004";
202*4882a593Smuzhiyun		reg = <0x49>;
203*4882a593Smuzhiyun		vio-supply = <&reg_3p3v>;
204*4882a593Smuzhiyun		pinctrl-names = "default";
205*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_tsc2004_hw300>;
206*4882a593Smuzhiyun		interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>;
207*4882a593Smuzhiyun		status = "disabled";
208*4882a593Smuzhiyun	};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun	eeprom@50 {
211*4882a593Smuzhiyun		compatible = "atmel,24c02";
212*4882a593Smuzhiyun		reg = <0x50>;
213*4882a593Smuzhiyun		pagesize = <16>;
214*4882a593Smuzhiyun	};
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun	rtc@56 {
217*4882a593Smuzhiyun		compatible = "microcrystal,rv3029";
218*4882a593Smuzhiyun		pinctrl-names = "default";
219*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_rtc_hw300>;
220*4882a593Smuzhiyun		reg = <0x56>;
221*4882a593Smuzhiyun		interrupt-parent = <&gpio7>;
222*4882a593Smuzhiyun		interrupts = <12 2>;
223*4882a593Smuzhiyun	};
224*4882a593Smuzhiyun};
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun&iomuxc {
227*4882a593Smuzhiyun	pinctrl-names = "default";
228*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_hog_base>;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun	pinctrl_hog_base: hog-base-grp {
231*4882a593Smuzhiyun		fsl,pins = <
232*4882a593Smuzhiyun			MX6QDL_PAD_EIM_A19__GPIO2_IO19		0x120b0
233*4882a593Smuzhiyun			MX6QDL_PAD_EIM_A23__GPIO6_IO06		0x120b0
234*4882a593Smuzhiyun			MX6QDL_PAD_EIM_A22__GPIO2_IO16		0x120b0
235*4882a593Smuzhiyun			MX6QDL_PAD_EIM_A16__GPIO2_IO22		0x120b0
236*4882a593Smuzhiyun			MX6QDL_PAD_EIM_A17__GPIO2_IO21		0x120b0
237*4882a593Smuzhiyun		>;
238*4882a593Smuzhiyun	};
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun	pinctrl_ecspi1: ecspi1-grp {
241*4882a593Smuzhiyun		fsl,pins = <
242*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
243*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
244*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
245*4882a593Smuzhiyun			MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x1b0b0
246*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11		0x1b0b0
247*4882a593Smuzhiyun		>;
248*4882a593Smuzhiyun	};
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun	pinctrl_ecspi2: ecspi2-grp {
251*4882a593Smuzhiyun		fsl,pins = <
252*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO	0x100b1
253*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI	0x100b1
254*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK	0x100b1
255*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29	0x1b0b0
256*4882a593Smuzhiyun		>;
257*4882a593Smuzhiyun	};
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun	pinctrl_enet_100M: enet-100M-grp {
260*4882a593Smuzhiyun		fsl,pins = <
261*4882a593Smuzhiyun			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
262*4882a593Smuzhiyun			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
263*4882a593Smuzhiyun			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
264*4882a593Smuzhiyun			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
265*4882a593Smuzhiyun			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
266*4882a593Smuzhiyun			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
267*4882a593Smuzhiyun			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
268*4882a593Smuzhiyun			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0
269*4882a593Smuzhiyun			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0
270*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
271*4882a593Smuzhiyun			MX6QDL_PAD_EIM_WAIT__GPIO5_IO00		0x000b0
272*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x000b1
273*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_7__GPIO1_IO07		0x120b0
274*4882a593Smuzhiyun		>;
275*4882a593Smuzhiyun	};
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun	pinctrl_flexcan1: flexcan1-grp {
278*4882a593Smuzhiyun		fsl,pins = <
279*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b0
280*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX		0x1b0b0
281*4882a593Smuzhiyun		>;
282*4882a593Smuzhiyun	};
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun	pinctrl_flexcan2: flexcan2-grp {
285*4882a593Smuzhiyun		fsl,pins = <
286*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX	0x1b0b0
287*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX	0x1b0b0
288*4882a593Smuzhiyun		>;
289*4882a593Smuzhiyun	};
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun	pinctrl_i2c1: i2c1-grp {
292*4882a593Smuzhiyun		fsl,pins = <
293*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
294*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
295*4882a593Smuzhiyun		>;
296*4882a593Smuzhiyun	};
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun	pinctrl_i2c1_gpio: i2c1-gpio-grp {
299*4882a593Smuzhiyun		fsl,pins = <
300*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D21__GPIO3_IO21		0x4001b8b1
301*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D28__GPIO3_IO28		0x4001b8b1
302*4882a593Smuzhiyun		>;
303*4882a593Smuzhiyun	};
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun	pinctrl_i2c2: i2c2-grp {
306*4882a593Smuzhiyun		fsl,pins = <
307*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
308*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
309*4882a593Smuzhiyun		>;
310*4882a593Smuzhiyun	};
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun	pinctrl_i2c2_gpio: i2c2-gpio-grp {
313*4882a593Smuzhiyun		fsl,pins = <
314*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL3__GPIO4_IO12		0x4001b8b1
315*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW3__GPIO4_IO13		0x4001b8b1
316*4882a593Smuzhiyun		>;
317*4882a593Smuzhiyun	};
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun	pinctrl_i2c3: i2c3-grp {
320*4882a593Smuzhiyun		fsl,pins = <
321*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
322*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
323*4882a593Smuzhiyun		>;
324*4882a593Smuzhiyun	};
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun	pinctrl_i2c3_gpio: i2c3-gpio-grp {
327*4882a593Smuzhiyun		fsl,pins = <
328*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_3__GPIO1_IO03		0x4001b8b1
329*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_6__GPIO1_IO06		0x4001b8b1
330*4882a593Smuzhiyun		>;
331*4882a593Smuzhiyun	};
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun	pinctrl_pmic_hw300: pmic-hw300-grp {
334*4882a593Smuzhiyun		fsl,pins = <
335*4882a593Smuzhiyun			MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x1B0B0
336*4882a593Smuzhiyun		>;
337*4882a593Smuzhiyun	};
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun	pinctrl_rtc_hw300: rtc-hw300-grp {
340*4882a593Smuzhiyun		fsl,pins = <
341*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x120B0
342*4882a593Smuzhiyun		>;
343*4882a593Smuzhiyun	};
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun	pinctrl_tsc2004_hw300: tsc2004-hw300-grp {
346*4882a593Smuzhiyun		fsl,pins = <
347*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL4__GPIO4_IO14		0x120B0
348*4882a593Smuzhiyun		>;
349*4882a593Smuzhiyun	};
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun	pinctrl_uart1: uart1-grp {
352*4882a593Smuzhiyun		fsl,pins = <
353*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
354*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
355*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D20__UART1_RTS_B		0x1b0b1
356*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D19__UART1_CTS_B		0x4001b0b1
357*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x4001b0b1
358*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D24__GPIO3_IO24		0x4001b0b1
359*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D25__GPIO3_IO25		0x4001b0b1
360*4882a593Smuzhiyun			MX6QDL_PAD_EIM_EB3__GPIO2_IO31		0x4001b0b1
361*4882a593Smuzhiyun		>;
362*4882a593Smuzhiyun	};
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun	pinctrl_uart4: uart4-grp {
365*4882a593Smuzhiyun		fsl,pins = <
366*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA	0x1b0b1
367*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA	0x1b0b1
368*4882a593Smuzhiyun		>;
369*4882a593Smuzhiyun	};
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun	pinctrl_uart5: uart5-grp {
372*4882a593Smuzhiyun		fsl,pins = <
373*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA	0x1b0b1
374*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA	0x1b0b1
375*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B	0x1b0b1
376*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B	0x4001b0b1
377*4882a593Smuzhiyun		>;
378*4882a593Smuzhiyun	};
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun	pinctrl_usbh1: usbh1-grp {
381*4882a593Smuzhiyun		fsl,pins = <
382*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x120B0
383*4882a593Smuzhiyun		>;
384*4882a593Smuzhiyun	};
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun	pinctrl_usbotg: usbotg-grp {
387*4882a593Smuzhiyun		fsl,pins = <
388*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
389*4882a593Smuzhiyun		>;
390*4882a593Smuzhiyun	};
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun	pinctrl_usdhc2: usdhc2-grp {
393*4882a593Smuzhiyun		fsl,pins = <
394*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
395*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
396*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
397*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
398*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
399*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
400*4882a593Smuzhiyun			MX6QDL_PAD_NANDF_CS3__GPIO6_IO16	0x120B0
401*4882a593Smuzhiyun		>;
402*4882a593Smuzhiyun	};
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun	pinctrl_usdhc3: usdhc3-grp {
405*4882a593Smuzhiyun		fsl,pins = <
406*4882a593Smuzhiyun			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
407*4882a593Smuzhiyun			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
408*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
409*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
410*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
411*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
412*4882a593Smuzhiyun			MX6QDL_PAD_SD3_RST__GPIO7_IO08		0x120B0
413*4882a593Smuzhiyun		>;
414*4882a593Smuzhiyun	};
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun	pinctrl_usdhc4: usdhc4-grp {
417*4882a593Smuzhiyun		fsl,pins = <
418*4882a593Smuzhiyun			MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
419*4882a593Smuzhiyun			MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
420*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
421*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
422*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
423*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
424*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059
425*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059
426*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059
427*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
428*4882a593Smuzhiyun		>;
429*4882a593Smuzhiyun	};
430*4882a593Smuzhiyun};
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun&reg_arm {
433*4882a593Smuzhiyun	vin-supply = <&sw3_reg>;
434*4882a593Smuzhiyun};
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun&reg_soc {
437*4882a593Smuzhiyun	vin-supply = <&sw1_reg>;
438*4882a593Smuzhiyun};
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun&reg_pu {
441*4882a593Smuzhiyun	vin-supply = <&sw1_reg>;
442*4882a593Smuzhiyun};
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun&reg_vdd1p1 {
445*4882a593Smuzhiyun	vin-supply = <&sw2_reg>;
446*4882a593Smuzhiyun};
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun&reg_vdd2p5 {
449*4882a593Smuzhiyun	vin-supply = <&sw2_reg>;
450*4882a593Smuzhiyun};
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun&uart1 {
453*4882a593Smuzhiyun	pinctrl-names = "default";
454*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
455*4882a593Smuzhiyun	uart-has-rtscts;
456*4882a593Smuzhiyun	dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
457*4882a593Smuzhiyun	dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
458*4882a593Smuzhiyun	dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
459*4882a593Smuzhiyun	rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
460*4882a593Smuzhiyun	status = "okay";
461*4882a593Smuzhiyun};
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun&uart4 {
464*4882a593Smuzhiyun	pinctrl-names = "default";
465*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart4>;
466*4882a593Smuzhiyun	status = "okay";
467*4882a593Smuzhiyun};
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun&uart5 {
470*4882a593Smuzhiyun	pinctrl-names = "default";
471*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart5>;
472*4882a593Smuzhiyun	uart-has-rtscts;
473*4882a593Smuzhiyun	status = "okay";
474*4882a593Smuzhiyun};
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun&usbh1 {
477*4882a593Smuzhiyun	pinctrl-names = "default";
478*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbh1>;
479*4882a593Smuzhiyun	vbus-supply = <&reg_usb_h1_vbus>;
480*4882a593Smuzhiyun	dr_mode = "host";
481*4882a593Smuzhiyun	status = "okay";
482*4882a593Smuzhiyun};
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun&usbotg {
485*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg_vbus>;
486*4882a593Smuzhiyun	pinctrl-names = "default";
487*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg>;
488*4882a593Smuzhiyun	disable-over-current;
489*4882a593Smuzhiyun	dr_mode = "otg";
490*4882a593Smuzhiyun	status = "okay";
491*4882a593Smuzhiyun};
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun&usdhc2 {
494*4882a593Smuzhiyun	pinctrl-names = "default";
495*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
496*4882a593Smuzhiyun	cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
497*4882a593Smuzhiyun	keep-power-in-suspend;
498*4882a593Smuzhiyun	status = "okay";
499*4882a593Smuzhiyun};
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun&usdhc3 {
502*4882a593Smuzhiyun	pinctrl-names = "default";
503*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc3>;
504*4882a593Smuzhiyun	cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
505*4882a593Smuzhiyun	fsl,wp-controller;
506*4882a593Smuzhiyun	keep-power-in-suspend;
507*4882a593Smuzhiyun	status = "disabled";
508*4882a593Smuzhiyun};
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun&usdhc4 {
511*4882a593Smuzhiyun	pinctrl-names = "default";
512*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc4>;
513*4882a593Smuzhiyun	non-removable;
514*4882a593Smuzhiyun	bus-width = <8>;
515*4882a593Smuzhiyun	no-1-8-v;
516*4882a593Smuzhiyun	keep-power-in-suspend;
517*4882a593Smuzhiyun	status = "okay";
518*4882a593Smuzhiyun};
519