1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 OR X11 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2015 Boundary Devices, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 6*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun chosen { 10*4882a593Smuzhiyun stdout-path = &uart2; 11*4882a593Smuzhiyun }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun memory@10000000 { 14*4882a593Smuzhiyun device_type = "memory"; 15*4882a593Smuzhiyun reg = <0x10000000 0xF0000000>; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun regulators { 19*4882a593Smuzhiyun compatible = "simple-bus"; 20*4882a593Smuzhiyun #address-cells = <1>; 21*4882a593Smuzhiyun #size-cells = <0>; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun reg_1p8v: regulator@0 { 24*4882a593Smuzhiyun compatible = "regulator-fixed"; 25*4882a593Smuzhiyun reg = <0>; 26*4882a593Smuzhiyun regulator-name = "1P8V"; 27*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 28*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 29*4882a593Smuzhiyun regulator-always-on; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun reg_2p5v: regulator@1 { 33*4882a593Smuzhiyun compatible = "regulator-fixed"; 34*4882a593Smuzhiyun reg = <1>; 35*4882a593Smuzhiyun regulator-name = "2P5V"; 36*4882a593Smuzhiyun regulator-min-microvolt = <2500000>; 37*4882a593Smuzhiyun regulator-max-microvolt = <2500000>; 38*4882a593Smuzhiyun regulator-always-on; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun reg_3p3v: regulator@2 { 42*4882a593Smuzhiyun compatible = "regulator-fixed"; 43*4882a593Smuzhiyun reg = <2>; 44*4882a593Smuzhiyun regulator-name = "3P3V"; 45*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 46*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 47*4882a593Smuzhiyun regulator-always-on; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun reg_usb_otg_vbus: regulator@3 { 51*4882a593Smuzhiyun compatible = "regulator-fixed"; 52*4882a593Smuzhiyun reg = <3>; 53*4882a593Smuzhiyun regulator-name = "usb_otg_vbus"; 54*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 55*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 56*4882a593Smuzhiyun gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 57*4882a593Smuzhiyun enable-active-high; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun reg_usb_h1_vbus: regulator@4 { 61*4882a593Smuzhiyun compatible = "regulator-fixed"; 62*4882a593Smuzhiyun reg = <4>; 63*4882a593Smuzhiyun pinctrl-names = "default"; 64*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbh1>; 65*4882a593Smuzhiyun regulator-name = "usb_h1_vbus"; 66*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 67*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 68*4882a593Smuzhiyun gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; 69*4882a593Smuzhiyun enable-active-high; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun reg_wlan_vmmc: regulator@5 { 73*4882a593Smuzhiyun compatible = "regulator-fixed"; 74*4882a593Smuzhiyun reg = <5>; 75*4882a593Smuzhiyun pinctrl-names = "default"; 76*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_wlan_vmmc>; 77*4882a593Smuzhiyun regulator-name = "reg_wlan_vmmc"; 78*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 79*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 80*4882a593Smuzhiyun gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; 81*4882a593Smuzhiyun startup-delay-us = <70000>; 82*4882a593Smuzhiyun enable-active-high; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun reg_can_xcvr: regulator@6 { 86*4882a593Smuzhiyun compatible = "regulator-fixed"; 87*4882a593Smuzhiyun reg = <6>; 88*4882a593Smuzhiyun regulator-name = "CAN XCVR"; 89*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 90*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 91*4882a593Smuzhiyun pinctrl-names = "default"; 92*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_can_xcvr>; 93*4882a593Smuzhiyun gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun gpio-keys { 98*4882a593Smuzhiyun compatible = "gpio-keys"; 99*4882a593Smuzhiyun pinctrl-names = "default"; 100*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_keys>; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun power { 103*4882a593Smuzhiyun label = "Power Button"; 104*4882a593Smuzhiyun gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; 105*4882a593Smuzhiyun linux,code = <KEY_POWER>; 106*4882a593Smuzhiyun wakeup-source; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun menu { 110*4882a593Smuzhiyun label = "Menu"; 111*4882a593Smuzhiyun gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 112*4882a593Smuzhiyun linux,code = <KEY_MENU>; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun home { 116*4882a593Smuzhiyun label = "Home"; 117*4882a593Smuzhiyun gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; 118*4882a593Smuzhiyun linux,code = <KEY_HOME>; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun back { 122*4882a593Smuzhiyun label = "Back"; 123*4882a593Smuzhiyun gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 124*4882a593Smuzhiyun linux,code = <KEY_BACK>; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun volume-up { 128*4882a593Smuzhiyun label = "Volume Up"; 129*4882a593Smuzhiyun gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; 130*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun volume-down { 134*4882a593Smuzhiyun label = "Volume Down"; 135*4882a593Smuzhiyun gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; 136*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun i2c2mux { 141*4882a593Smuzhiyun compatible = "i2c-mux-gpio"; 142*4882a593Smuzhiyun pinctrl-names = "default"; 143*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2mux>; 144*4882a593Smuzhiyun #address-cells = <1>; 145*4882a593Smuzhiyun #size-cells = <0>; 146*4882a593Smuzhiyun mux-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH 147*4882a593Smuzhiyun &gpio4 15 GPIO_ACTIVE_HIGH>; 148*4882a593Smuzhiyun i2c-parent = <&i2c2>; 149*4882a593Smuzhiyun idle-state = <0>; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun i2c2mux@1 { 152*4882a593Smuzhiyun reg = <1>; 153*4882a593Smuzhiyun #address-cells = <1>; 154*4882a593Smuzhiyun #size-cells = <0>; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun i2c2mux@2 { 158*4882a593Smuzhiyun reg = <2>; 159*4882a593Smuzhiyun #address-cells = <1>; 160*4882a593Smuzhiyun #size-cells = <0>; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun i2c3mux { 165*4882a593Smuzhiyun compatible = "i2c-mux-gpio"; 166*4882a593Smuzhiyun pinctrl-names = "default"; 167*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3mux>; 168*4882a593Smuzhiyun #address-cells = <1>; 169*4882a593Smuzhiyun #size-cells = <0>; 170*4882a593Smuzhiyun mux-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; 171*4882a593Smuzhiyun i2c-parent = <&i2c3>; 172*4882a593Smuzhiyun idle-state = <0>; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun i2c3mux@1 { 175*4882a593Smuzhiyun reg = <1>; 176*4882a593Smuzhiyun #address-cells = <1>; 177*4882a593Smuzhiyun #size-cells = <0>; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun leds { 182*4882a593Smuzhiyun compatible = "gpio-leds"; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun speaker-enable { 185*4882a593Smuzhiyun gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; 186*4882a593Smuzhiyun retain-state-suspended; 187*4882a593Smuzhiyun default-state = "off"; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun ttymxc4-rs232 { 191*4882a593Smuzhiyun gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; 192*4882a593Smuzhiyun retain-state-suspended; 193*4882a593Smuzhiyun default-state = "on"; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun backlight_lcd: backlight-lcd { 198*4882a593Smuzhiyun compatible = "pwm-backlight"; 199*4882a593Smuzhiyun pwms = <&pwm1 0 5000000>; 200*4882a593Smuzhiyun brightness-levels = <0 4 8 16 32 64 128 255>; 201*4882a593Smuzhiyun default-brightness-level = <7>; 202*4882a593Smuzhiyun power-supply = <®_3p3v>; 203*4882a593Smuzhiyun status = "okay"; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun backlight_lvds0: backlight-lvds0 { 207*4882a593Smuzhiyun compatible = "pwm-backlight"; 208*4882a593Smuzhiyun pwms = <&pwm4 0 5000000>; 209*4882a593Smuzhiyun brightness-levels = <0 4 8 16 32 64 128 255>; 210*4882a593Smuzhiyun default-brightness-level = <7>; 211*4882a593Smuzhiyun power-supply = <®_3p3v>; 212*4882a593Smuzhiyun status = "okay"; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun backlight_lvds1: backlight-lvds1 { 216*4882a593Smuzhiyun compatible = "pwm-backlight"; 217*4882a593Smuzhiyun pwms = <&pwm2 0 5000000>; 218*4882a593Smuzhiyun brightness-levels = <0 4 8 16 32 64 128 255>; 219*4882a593Smuzhiyun default-brightness-level = <7>; 220*4882a593Smuzhiyun power-supply = <®_3p3v>; 221*4882a593Smuzhiyun status = "okay"; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun lcd_display: disp0 { 225*4882a593Smuzhiyun compatible = "fsl,imx-parallel-display"; 226*4882a593Smuzhiyun #address-cells = <1>; 227*4882a593Smuzhiyun #size-cells = <0>; 228*4882a593Smuzhiyun interface-pix-fmt = "bgr666"; 229*4882a593Smuzhiyun pinctrl-names = "default"; 230*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_j15>; 231*4882a593Smuzhiyun status = "okay"; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun port@0 { 234*4882a593Smuzhiyun reg = <0>; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun lcd_display_in: endpoint { 237*4882a593Smuzhiyun remote-endpoint = <&ipu1_di0_disp0>; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun port@1 { 242*4882a593Smuzhiyun reg = <1>; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun lcd_display_out: endpoint { 245*4882a593Smuzhiyun remote-endpoint = <&lcd_panel_in>; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun }; 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun panel-lcd { 251*4882a593Smuzhiyun compatible = "okaya,rs800480t-7x0gp"; 252*4882a593Smuzhiyun backlight = <&backlight_lcd>; 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun port { 255*4882a593Smuzhiyun lcd_panel_in: endpoint { 256*4882a593Smuzhiyun remote-endpoint = <&lcd_display_out>; 257*4882a593Smuzhiyun }; 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun }; 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun panel-lvds0 { 262*4882a593Smuzhiyun compatible = "hannstar,hsd100pxn1"; 263*4882a593Smuzhiyun backlight = <&backlight_lvds0>; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun port { 266*4882a593Smuzhiyun panel_in_lvds0: endpoint { 267*4882a593Smuzhiyun remote-endpoint = <&lvds0_out>; 268*4882a593Smuzhiyun }; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun }; 271*4882a593Smuzhiyun 272*4882a593Smuzhiyun panel-lvds1 { 273*4882a593Smuzhiyun compatible = "hannstar,hsd100pxn1"; 274*4882a593Smuzhiyun backlight = <&backlight_lvds1>; 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun port { 277*4882a593Smuzhiyun panel_in_lvds1: endpoint { 278*4882a593Smuzhiyun remote-endpoint = <&lvds1_out>; 279*4882a593Smuzhiyun }; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun sound { 284*4882a593Smuzhiyun compatible = "fsl,imx6q-nitrogen6_max-sgtl5000", 285*4882a593Smuzhiyun "fsl,imx-audio-sgtl5000"; 286*4882a593Smuzhiyun model = "imx6q-nitrogen6_max-sgtl5000"; 287*4882a593Smuzhiyun ssi-controller = <&ssi1>; 288*4882a593Smuzhiyun audio-codec = <&codec>; 289*4882a593Smuzhiyun audio-routing = 290*4882a593Smuzhiyun "MIC_IN", "Mic Jack", 291*4882a593Smuzhiyun "Mic Jack", "Mic Bias", 292*4882a593Smuzhiyun "Headphone Jack", "HP_OUT"; 293*4882a593Smuzhiyun mux-int-port = <1>; 294*4882a593Smuzhiyun mux-ext-port = <3>; 295*4882a593Smuzhiyun }; 296*4882a593Smuzhiyun}; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun&audmux { 299*4882a593Smuzhiyun pinctrl-names = "default"; 300*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_audmux>; 301*4882a593Smuzhiyun status = "okay"; 302*4882a593Smuzhiyun}; 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun&can1 { 305*4882a593Smuzhiyun pinctrl-names = "default"; 306*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_can1>; 307*4882a593Smuzhiyun xceiver-supply = <®_can_xcvr>; 308*4882a593Smuzhiyun status = "okay"; 309*4882a593Smuzhiyun}; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun&clks { 312*4882a593Smuzhiyun assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 313*4882a593Smuzhiyun <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 314*4882a593Smuzhiyun assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 315*4882a593Smuzhiyun <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 316*4882a593Smuzhiyun}; 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun&ecspi1 { 319*4882a593Smuzhiyun cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; 320*4882a593Smuzhiyun pinctrl-names = "default"; 321*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ecspi1>; 322*4882a593Smuzhiyun status = "okay"; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun flash: flash@0 { 325*4882a593Smuzhiyun compatible = "microchip,sst25vf016b"; 326*4882a593Smuzhiyun spi-max-frequency = <20000000>; 327*4882a593Smuzhiyun reg = <0>; 328*4882a593Smuzhiyun }; 329*4882a593Smuzhiyun}; 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun&fec { 332*4882a593Smuzhiyun pinctrl-names = "default"; 333*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet>; 334*4882a593Smuzhiyun phy-mode = "rgmii"; 335*4882a593Smuzhiyun phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; 336*4882a593Smuzhiyun txen-skew-ps = <0>; 337*4882a593Smuzhiyun txc-skew-ps = <3000>; 338*4882a593Smuzhiyun rxdv-skew-ps = <0>; 339*4882a593Smuzhiyun rxc-skew-ps = <3000>; 340*4882a593Smuzhiyun rxd0-skew-ps = <0>; 341*4882a593Smuzhiyun rxd1-skew-ps = <0>; 342*4882a593Smuzhiyun rxd2-skew-ps = <0>; 343*4882a593Smuzhiyun rxd3-skew-ps = <0>; 344*4882a593Smuzhiyun txd0-skew-ps = <0>; 345*4882a593Smuzhiyun txd1-skew-ps = <0>; 346*4882a593Smuzhiyun txd2-skew-ps = <0>; 347*4882a593Smuzhiyun txd3-skew-ps = <0>; 348*4882a593Smuzhiyun interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, 349*4882a593Smuzhiyun <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; 350*4882a593Smuzhiyun fsl,err006687-workaround-present; 351*4882a593Smuzhiyun status = "okay"; 352*4882a593Smuzhiyun}; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun&hdmi { 355*4882a593Smuzhiyun ddc-i2c-bus = <&i2c2>; 356*4882a593Smuzhiyun status = "okay"; 357*4882a593Smuzhiyun}; 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun&i2c1 { 360*4882a593Smuzhiyun clock-frequency = <100000>; 361*4882a593Smuzhiyun pinctrl-names = "default"; 362*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 363*4882a593Smuzhiyun status = "okay"; 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun codec: sgtl5000@a { 366*4882a593Smuzhiyun compatible = "fsl,sgtl5000"; 367*4882a593Smuzhiyun pinctrl-names = "default"; 368*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_sgtl5000>; 369*4882a593Smuzhiyun reg = <0x0a>; 370*4882a593Smuzhiyun clocks = <&clks IMX6QDL_CLK_CKO>; 371*4882a593Smuzhiyun VDDA-supply = <®_2p5v>; 372*4882a593Smuzhiyun VDDIO-supply = <®_3p3v>; 373*4882a593Smuzhiyun }; 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun rtc: rtc@68 { 376*4882a593Smuzhiyun compatible = "microcrystal,rv4162"; 377*4882a593Smuzhiyun pinctrl-names = "default"; 378*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_rv4162>; 379*4882a593Smuzhiyun reg = <0x68>; 380*4882a593Smuzhiyun interrupts-extended = <&gpio4 6 IRQ_TYPE_LEVEL_LOW>; 381*4882a593Smuzhiyun }; 382*4882a593Smuzhiyun}; 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun&i2c2 { 385*4882a593Smuzhiyun clock-frequency = <100000>; 386*4882a593Smuzhiyun pinctrl-names = "default"; 387*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 388*4882a593Smuzhiyun status = "okay"; 389*4882a593Smuzhiyun}; 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun&i2c3 { 392*4882a593Smuzhiyun clock-frequency = <100000>; 393*4882a593Smuzhiyun pinctrl-names = "default"; 394*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 395*4882a593Smuzhiyun status = "okay"; 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun touchscreen@4 { 398*4882a593Smuzhiyun compatible = "eeti,egalax_ts"; 399*4882a593Smuzhiyun reg = <0x04>; 400*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 401*4882a593Smuzhiyun interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 402*4882a593Smuzhiyun wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 403*4882a593Smuzhiyun }; 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun touchscreen@38 { 406*4882a593Smuzhiyun compatible = "edt,edt-ft5x06"; 407*4882a593Smuzhiyun reg = <0x38>; 408*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 409*4882a593Smuzhiyun interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 410*4882a593Smuzhiyun wakeup-source; 411*4882a593Smuzhiyun }; 412*4882a593Smuzhiyun}; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun&iomuxc { 415*4882a593Smuzhiyun imx6q-nitrogen6-max { 416*4882a593Smuzhiyun pinctrl_audmux: audmuxgrp { 417*4882a593Smuzhiyun fsl,pins = < 418*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 419*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 420*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 421*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 422*4882a593Smuzhiyun >; 423*4882a593Smuzhiyun }; 424*4882a593Smuzhiyun 425*4882a593Smuzhiyun pinctrl_can1: can1grp { 426*4882a593Smuzhiyun fsl,pins = < 427*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 428*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 429*4882a593Smuzhiyun >; 430*4882a593Smuzhiyun }; 431*4882a593Smuzhiyun 432*4882a593Smuzhiyun pinctrl_can_xcvr: can-xcvrgrp { 433*4882a593Smuzhiyun fsl,pins = < 434*4882a593Smuzhiyun /* Flexcan XCVR enable */ 435*4882a593Smuzhiyun MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 436*4882a593Smuzhiyun >; 437*4882a593Smuzhiyun }; 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun pinctrl_ecspi1: ecspi1grp { 440*4882a593Smuzhiyun fsl,pins = < 441*4882a593Smuzhiyun MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 442*4882a593Smuzhiyun MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 443*4882a593Smuzhiyun MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 444*4882a593Smuzhiyun MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 445*4882a593Smuzhiyun >; 446*4882a593Smuzhiyun }; 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun pinctrl_enet: enetgrp { 449*4882a593Smuzhiyun fsl,pins = < 450*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 451*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 452*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 453*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 454*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 455*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 456*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 457*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 458*4882a593Smuzhiyun MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 459*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 460*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 461*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 462*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 463*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 464*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 465*4882a593Smuzhiyun /* Phy reset */ 466*4882a593Smuzhiyun MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 467*4882a593Smuzhiyun MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 468*4882a593Smuzhiyun MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 469*4882a593Smuzhiyun >; 470*4882a593Smuzhiyun }; 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun pinctrl_gpio_keys: gpio-keysgrp { 473*4882a593Smuzhiyun fsl,pins = < 474*4882a593Smuzhiyun /* Power Button */ 475*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 476*4882a593Smuzhiyun /* Menu Button */ 477*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 478*4882a593Smuzhiyun /* Home Button */ 479*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 480*4882a593Smuzhiyun /* Back Button */ 481*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 482*4882a593Smuzhiyun /* Volume Up Button */ 483*4882a593Smuzhiyun MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 484*4882a593Smuzhiyun /* Volume Down Button */ 485*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 486*4882a593Smuzhiyun >; 487*4882a593Smuzhiyun }; 488*4882a593Smuzhiyun 489*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 490*4882a593Smuzhiyun fsl,pins = < 491*4882a593Smuzhiyun MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 492*4882a593Smuzhiyun MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 493*4882a593Smuzhiyun >; 494*4882a593Smuzhiyun }; 495*4882a593Smuzhiyun 496*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 497*4882a593Smuzhiyun fsl,pins = < 498*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 499*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 500*4882a593Smuzhiyun >; 501*4882a593Smuzhiyun }; 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun pinctrl_i2c2mux: i2c2muxgrp { 504*4882a593Smuzhiyun fsl,pins = < 505*4882a593Smuzhiyun /* ov5642 camera i2c enable */ 506*4882a593Smuzhiyun MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b0 507*4882a593Smuzhiyun /* ov5640_mipi camera i2c enable */ 508*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 509*4882a593Smuzhiyun >; 510*4882a593Smuzhiyun }; 511*4882a593Smuzhiyun 512*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 513*4882a593Smuzhiyun fsl,pins = < 514*4882a593Smuzhiyun MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 515*4882a593Smuzhiyun MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 516*4882a593Smuzhiyun MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 517*4882a593Smuzhiyun >; 518*4882a593Smuzhiyun }; 519*4882a593Smuzhiyun 520*4882a593Smuzhiyun pinctrl_i2c3mux: i2c3muxgrp { 521*4882a593Smuzhiyun fsl,pins = < 522*4882a593Smuzhiyun /* PCIe I2C enable */ 523*4882a593Smuzhiyun MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 524*4882a593Smuzhiyun >; 525*4882a593Smuzhiyun }; 526*4882a593Smuzhiyun 527*4882a593Smuzhiyun pinctrl_j15: j15grp { 528*4882a593Smuzhiyun fsl,pins = < 529*4882a593Smuzhiyun MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 530*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 531*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 532*4882a593Smuzhiyun MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 533*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 534*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 535*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 536*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 537*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 538*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 539*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 540*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 541*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 542*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 543*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 544*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 545*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 546*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 547*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 548*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 549*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 550*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 551*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 552*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 553*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 554*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 555*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 556*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 557*4882a593Smuzhiyun >; 558*4882a593Smuzhiyun }; 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun pinctrl_pcie: pciegrp { 561*4882a593Smuzhiyun fsl,pins = < 562*4882a593Smuzhiyun /* PCIe reset */ 563*4882a593Smuzhiyun MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0 564*4882a593Smuzhiyun >; 565*4882a593Smuzhiyun }; 566*4882a593Smuzhiyun 567*4882a593Smuzhiyun pinctrl_pwm1: pwm1grp { 568*4882a593Smuzhiyun fsl,pins = < 569*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 570*4882a593Smuzhiyun >; 571*4882a593Smuzhiyun }; 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun pinctrl_pwm2: pwm2grp { 574*4882a593Smuzhiyun fsl,pins = < 575*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 576*4882a593Smuzhiyun >; 577*4882a593Smuzhiyun }; 578*4882a593Smuzhiyun 579*4882a593Smuzhiyun pinctrl_pwm3: pwm3grp { 580*4882a593Smuzhiyun fsl,pins = < 581*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 582*4882a593Smuzhiyun >; 583*4882a593Smuzhiyun }; 584*4882a593Smuzhiyun 585*4882a593Smuzhiyun pinctrl_pwm4: pwm4grp { 586*4882a593Smuzhiyun fsl,pins = < 587*4882a593Smuzhiyun MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 588*4882a593Smuzhiyun >; 589*4882a593Smuzhiyun }; 590*4882a593Smuzhiyun 591*4882a593Smuzhiyun pinctrl_rv4162: rv4162grp { 592*4882a593Smuzhiyun fsl,pins = < 593*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 594*4882a593Smuzhiyun >; 595*4882a593Smuzhiyun }; 596*4882a593Smuzhiyun 597*4882a593Smuzhiyun pinctrl_sgtl5000: sgtl5000grp { 598*4882a593Smuzhiyun fsl,pins = < 599*4882a593Smuzhiyun MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 600*4882a593Smuzhiyun MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 601*4882a593Smuzhiyun MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 602*4882a593Smuzhiyun >; 603*4882a593Smuzhiyun }; 604*4882a593Smuzhiyun 605*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 606*4882a593Smuzhiyun fsl,pins = < 607*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 608*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 609*4882a593Smuzhiyun >; 610*4882a593Smuzhiyun }; 611*4882a593Smuzhiyun 612*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 613*4882a593Smuzhiyun fsl,pins = < 614*4882a593Smuzhiyun MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 615*4882a593Smuzhiyun MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 616*4882a593Smuzhiyun >; 617*4882a593Smuzhiyun }; 618*4882a593Smuzhiyun 619*4882a593Smuzhiyun pinctrl_uart5: uart5grp { 620*4882a593Smuzhiyun fsl,pins = < 621*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x130b1 622*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x030b1 623*4882a593Smuzhiyun /* RS485 RX Enable: pull up */ 624*4882a593Smuzhiyun MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b1 625*4882a593Smuzhiyun /* RS485 DEN: pull down */ 626*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b1 627*4882a593Smuzhiyun /* RS485/!RS232 Select: pull down (rs232) */ 628*4882a593Smuzhiyun MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b1 629*4882a593Smuzhiyun /* ON: pull down */ 630*4882a593Smuzhiyun MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b1 631*4882a593Smuzhiyun >; 632*4882a593Smuzhiyun }; 633*4882a593Smuzhiyun 634*4882a593Smuzhiyun pinctrl_usbh1: usbh1grp { 635*4882a593Smuzhiyun fsl,pins = < 636*4882a593Smuzhiyun MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 637*4882a593Smuzhiyun >; 638*4882a593Smuzhiyun }; 639*4882a593Smuzhiyun 640*4882a593Smuzhiyun pinctrl_usbotg: usbotggrp { 641*4882a593Smuzhiyun fsl,pins = < 642*4882a593Smuzhiyun MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 643*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 644*4882a593Smuzhiyun /* power enable, high active */ 645*4882a593Smuzhiyun MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 646*4882a593Smuzhiyun >; 647*4882a593Smuzhiyun }; 648*4882a593Smuzhiyun 649*4882a593Smuzhiyun pinctrl_usdhc2: usdhc2grp { 650*4882a593Smuzhiyun fsl,pins = < 651*4882a593Smuzhiyun MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 652*4882a593Smuzhiyun MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 653*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 654*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 655*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 656*4882a593Smuzhiyun MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 657*4882a593Smuzhiyun >; 658*4882a593Smuzhiyun }; 659*4882a593Smuzhiyun 660*4882a593Smuzhiyun pinctrl_usdhc3: usdhc3grp { 661*4882a593Smuzhiyun fsl,pins = < 662*4882a593Smuzhiyun MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 663*4882a593Smuzhiyun MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 664*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 665*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 666*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 667*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 668*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x100b0 669*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 670*4882a593Smuzhiyun >; 671*4882a593Smuzhiyun }; 672*4882a593Smuzhiyun 673*4882a593Smuzhiyun pinctrl_usdhc4: usdhc4grp { 674*4882a593Smuzhiyun fsl,pins = < 675*4882a593Smuzhiyun MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 676*4882a593Smuzhiyun MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 677*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 678*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 679*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 680*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 681*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 682*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 683*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 684*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 685*4882a593Smuzhiyun >; 686*4882a593Smuzhiyun }; 687*4882a593Smuzhiyun 688*4882a593Smuzhiyun pinctrl_wlan_vmmc: wlan-vmmcgrp { 689*4882a593Smuzhiyun fsl,pins = < 690*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 691*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 692*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 693*4882a593Smuzhiyun MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 694*4882a593Smuzhiyun >; 695*4882a593Smuzhiyun }; 696*4882a593Smuzhiyun }; 697*4882a593Smuzhiyun}; 698*4882a593Smuzhiyun 699*4882a593Smuzhiyun&ipu1_di0_disp0 { 700*4882a593Smuzhiyun remote-endpoint = <&lcd_display_in>; 701*4882a593Smuzhiyun}; 702*4882a593Smuzhiyun 703*4882a593Smuzhiyun&ldb { 704*4882a593Smuzhiyun status = "okay"; 705*4882a593Smuzhiyun 706*4882a593Smuzhiyun lvds-channel@0 { 707*4882a593Smuzhiyun status = "okay"; 708*4882a593Smuzhiyun 709*4882a593Smuzhiyun port@4 { 710*4882a593Smuzhiyun reg = <4>; 711*4882a593Smuzhiyun 712*4882a593Smuzhiyun lvds0_out: endpoint { 713*4882a593Smuzhiyun remote-endpoint = <&panel_in_lvds0>; 714*4882a593Smuzhiyun }; 715*4882a593Smuzhiyun }; 716*4882a593Smuzhiyun }; 717*4882a593Smuzhiyun 718*4882a593Smuzhiyun lvds-channel@1 { 719*4882a593Smuzhiyun status = "okay"; 720*4882a593Smuzhiyun 721*4882a593Smuzhiyun port@4 { 722*4882a593Smuzhiyun reg = <4>; 723*4882a593Smuzhiyun 724*4882a593Smuzhiyun lvds1_out: endpoint { 725*4882a593Smuzhiyun remote-endpoint = <&panel_in_lvds1>; 726*4882a593Smuzhiyun }; 727*4882a593Smuzhiyun }; 728*4882a593Smuzhiyun }; 729*4882a593Smuzhiyun}; 730*4882a593Smuzhiyun 731*4882a593Smuzhiyun&pcie { 732*4882a593Smuzhiyun pinctrl-names = "default"; 733*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pcie>; 734*4882a593Smuzhiyun reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>; 735*4882a593Smuzhiyun status = "okay"; 736*4882a593Smuzhiyun}; 737*4882a593Smuzhiyun 738*4882a593Smuzhiyun&pwm1 { 739*4882a593Smuzhiyun #pwm-cells = <2>; 740*4882a593Smuzhiyun pinctrl-names = "default"; 741*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm1>; 742*4882a593Smuzhiyun status = "okay"; 743*4882a593Smuzhiyun}; 744*4882a593Smuzhiyun 745*4882a593Smuzhiyun&pwm2 { 746*4882a593Smuzhiyun #pwm-cells = <2>; 747*4882a593Smuzhiyun pinctrl-names = "default"; 748*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm2>; 749*4882a593Smuzhiyun status = "okay"; 750*4882a593Smuzhiyun}; 751*4882a593Smuzhiyun 752*4882a593Smuzhiyun&pwm3 { 753*4882a593Smuzhiyun pinctrl-names = "default"; 754*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm3>; 755*4882a593Smuzhiyun status = "okay"; 756*4882a593Smuzhiyun}; 757*4882a593Smuzhiyun 758*4882a593Smuzhiyun&pwm4 { 759*4882a593Smuzhiyun #pwm-cells = <2>; 760*4882a593Smuzhiyun pinctrl-names = "default"; 761*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm4>; 762*4882a593Smuzhiyun status = "okay"; 763*4882a593Smuzhiyun}; 764*4882a593Smuzhiyun 765*4882a593Smuzhiyun&ssi1 { 766*4882a593Smuzhiyun status = "okay"; 767*4882a593Smuzhiyun}; 768*4882a593Smuzhiyun 769*4882a593Smuzhiyun&uart1 { 770*4882a593Smuzhiyun pinctrl-names = "default"; 771*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 772*4882a593Smuzhiyun status = "okay"; 773*4882a593Smuzhiyun}; 774*4882a593Smuzhiyun 775*4882a593Smuzhiyun&uart2 { 776*4882a593Smuzhiyun pinctrl-names = "default"; 777*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 778*4882a593Smuzhiyun status = "okay"; 779*4882a593Smuzhiyun}; 780*4882a593Smuzhiyun 781*4882a593Smuzhiyun&uart5 { 782*4882a593Smuzhiyun pinctrl-names = "default"; 783*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart5>; 784*4882a593Smuzhiyun status = "okay"; 785*4882a593Smuzhiyun}; 786*4882a593Smuzhiyun 787*4882a593Smuzhiyun&usbh1 { 788*4882a593Smuzhiyun vbus-supply = <®_usb_h1_vbus>; 789*4882a593Smuzhiyun status = "okay"; 790*4882a593Smuzhiyun}; 791*4882a593Smuzhiyun 792*4882a593Smuzhiyun&usbotg { 793*4882a593Smuzhiyun vbus-supply = <®_usb_otg_vbus>; 794*4882a593Smuzhiyun pinctrl-names = "default"; 795*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotg>; 796*4882a593Smuzhiyun disable-over-current; 797*4882a593Smuzhiyun status = "okay"; 798*4882a593Smuzhiyun}; 799*4882a593Smuzhiyun 800*4882a593Smuzhiyun&usdhc2 { 801*4882a593Smuzhiyun pinctrl-names = "default"; 802*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc2>; 803*4882a593Smuzhiyun bus-width = <4>; 804*4882a593Smuzhiyun non-removable; 805*4882a593Smuzhiyun vmmc-supply = <®_wlan_vmmc>; 806*4882a593Smuzhiyun cap-power-off-card; 807*4882a593Smuzhiyun keep-power-in-suspend; 808*4882a593Smuzhiyun status = "okay"; 809*4882a593Smuzhiyun 810*4882a593Smuzhiyun #address-cells = <1>; 811*4882a593Smuzhiyun #size-cells = <0>; 812*4882a593Smuzhiyun wlcore: wlcore@2 { 813*4882a593Smuzhiyun compatible = "ti,wl1271"; 814*4882a593Smuzhiyun reg = <2>; 815*4882a593Smuzhiyun interrupt-parent = <&gpio6>; 816*4882a593Smuzhiyun interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 817*4882a593Smuzhiyun ref-clock-frequency = <38400000>; 818*4882a593Smuzhiyun }; 819*4882a593Smuzhiyun}; 820*4882a593Smuzhiyun 821*4882a593Smuzhiyun&usdhc3 { 822*4882a593Smuzhiyun pinctrl-names = "default"; 823*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3>; 824*4882a593Smuzhiyun cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 825*4882a593Smuzhiyun bus-width = <4>; 826*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 827*4882a593Smuzhiyun status = "okay"; 828*4882a593Smuzhiyun}; 829*4882a593Smuzhiyun 830*4882a593Smuzhiyun&usdhc4 { 831*4882a593Smuzhiyun pinctrl-names = "default"; 832*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc4>; 833*4882a593Smuzhiyun bus-width = <8>; 834*4882a593Smuzhiyun non-removable; 835*4882a593Smuzhiyun vmmc-supply = <®_1p8v>; 836*4882a593Smuzhiyun keep-power-in-suspend; 837*4882a593Smuzhiyun status = "okay"; 838*4882a593Smuzhiyun}; 839