xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx6q-marsboard.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright (C) 2016 Sergio Prado (sergio.prado@e-labworks.com)
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms
5*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual
6*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a
7*4882a593Smuzhiyun * whole.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun *  a) This file is free software; you can redistribute it and/or
10*4882a593Smuzhiyun *     modify it under the terms of the GNU General Public License
11*4882a593Smuzhiyun *     version 2 as published by the Free Software Foundation.
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun *     This file is distributed in the hope that it will be useful,
14*4882a593Smuzhiyun *     but WITHOUT ANY WARRANTY; without even the implied warranty of
15*4882a593Smuzhiyun *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16*4882a593Smuzhiyun *     GNU General Public License for more details.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * Or, alternatively,
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun *  b) Permission is hereby granted, free of charge, to any person
21*4882a593Smuzhiyun *     obtaining a copy of this software and associated documentation
22*4882a593Smuzhiyun *     files (the "Software"), to deal in the Software without
23*4882a593Smuzhiyun *     restriction, including without limitation the rights to use,
24*4882a593Smuzhiyun *     copy, modify, merge, publish, distribute, sublicense, and/or
25*4882a593Smuzhiyun *     sell copies of the Software, and to permit persons to whom the
26*4882a593Smuzhiyun *     Software is furnished to do so, subject to the following
27*4882a593Smuzhiyun *     conditions:
28*4882a593Smuzhiyun *
29*4882a593Smuzhiyun *     The above copyright notice and this permission notice shall be
30*4882a593Smuzhiyun *     included in all copies or substantial portions of the Software.
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33*4882a593Smuzhiyun *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34*4882a593Smuzhiyun *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35*4882a593Smuzhiyun *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36*4882a593Smuzhiyun *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37*4882a593Smuzhiyun *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38*4882a593Smuzhiyun *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39*4882a593Smuzhiyun *     OTHER DEALINGS IN THE SOFTWARE.
40*4882a593Smuzhiyun */
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun/dts-v1/;
43*4882a593Smuzhiyun#include "imx6q.dtsi"
44*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun/ {
47*4882a593Smuzhiyun	model = "Embest MarS Board i.MX6Dual";
48*4882a593Smuzhiyun	compatible = "embest,imx6q-marsboard", "fsl,imx6q";
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun	memory@10000000 {
51*4882a593Smuzhiyun		device_type = "memory";
52*4882a593Smuzhiyun		reg = <0x10000000 0x40000000>;
53*4882a593Smuzhiyun	};
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun	reg_3p3v: regulator-3p3v {
56*4882a593Smuzhiyun		compatible = "regulator-fixed";
57*4882a593Smuzhiyun		regulator-name = "3P3V";
58*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
59*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
60*4882a593Smuzhiyun	};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun	reg_usb_otg_vbus: regulator-usb-otg-vbus {
63*4882a593Smuzhiyun		compatible = "regulator-fixed";
64*4882a593Smuzhiyun		regulator-name = "usb_otg_vbus";
65*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
66*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
67*4882a593Smuzhiyun		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
68*4882a593Smuzhiyun		enable-active-high;
69*4882a593Smuzhiyun	};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun	leds {
72*4882a593Smuzhiyun		compatible = "gpio-leds";
73*4882a593Smuzhiyun		pinctrl-names = "default";
74*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_led>;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun		user1 {
77*4882a593Smuzhiyun			label = "imx6:green:user1";
78*4882a593Smuzhiyun			gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
79*4882a593Smuzhiyun			default-state = "off";
80*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
81*4882a593Smuzhiyun		};
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun		user2 {
84*4882a593Smuzhiyun			label = "imx6:green:user2";
85*4882a593Smuzhiyun			gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
86*4882a593Smuzhiyun			default-state = "off";
87*4882a593Smuzhiyun		};
88*4882a593Smuzhiyun	};
89*4882a593Smuzhiyun};
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun&audmux {
92*4882a593Smuzhiyun	pinctrl-names = "default";
93*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_audmux>;
94*4882a593Smuzhiyun	status = "okay";
95*4882a593Smuzhiyun};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun&ecspi1 {
98*4882a593Smuzhiyun	pinctrl-names = "default";
99*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
100*4882a593Smuzhiyun	cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
101*4882a593Smuzhiyun	status = "okay";
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun	flash@0 {
104*4882a593Smuzhiyun		compatible = "microchip,sst25vf016b";
105*4882a593Smuzhiyun		spi-max-frequency = <20000000>;
106*4882a593Smuzhiyun		reg = <0>;
107*4882a593Smuzhiyun	};
108*4882a593Smuzhiyun};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun&fec {
111*4882a593Smuzhiyun	pinctrl-names = "default";
112*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet>;
113*4882a593Smuzhiyun	phy-mode = "rgmii-id";
114*4882a593Smuzhiyun	phy-handle = <&rgmii_phy>;
115*4882a593Smuzhiyun	status = "okay";
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun	mdio {
118*4882a593Smuzhiyun		#address-cells = <1>;
119*4882a593Smuzhiyun		#size-cells = <0>;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun		/* Atheros AR8035 PHY */
122*4882a593Smuzhiyun		rgmii_phy: ethernet-phy@4 {
123*4882a593Smuzhiyun			reg = <4>;
124*4882a593Smuzhiyun			interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
125*4882a593Smuzhiyun			reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
126*4882a593Smuzhiyun			reset-assert-us = <10000>;
127*4882a593Smuzhiyun			reset-deassert-us = <1000>;
128*4882a593Smuzhiyun		};
129*4882a593Smuzhiyun	};
130*4882a593Smuzhiyun};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun&hdmi {
133*4882a593Smuzhiyun	ddc-i2c-bus = <&i2c2>;
134*4882a593Smuzhiyun	status = "okay";
135*4882a593Smuzhiyun};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun&i2c1 {
138*4882a593Smuzhiyun	clock-frequency = <100000>;
139*4882a593Smuzhiyun	pinctrl-names = "default";
140*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
141*4882a593Smuzhiyun	status = "okay";
142*4882a593Smuzhiyun};
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun&i2c2 {
145*4882a593Smuzhiyun	clock-frequency = <100000>;
146*4882a593Smuzhiyun	pinctrl-names = "default";
147*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
148*4882a593Smuzhiyun	status = "okay";
149*4882a593Smuzhiyun};
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun&i2c3 {
152*4882a593Smuzhiyun	clock-frequency = <100000>;
153*4882a593Smuzhiyun	pinctrl-names = "default";
154*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c3>;
155*4882a593Smuzhiyun	status = "okay";
156*4882a593Smuzhiyun};
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun&pwm1 {
159*4882a593Smuzhiyun	pinctrl-names = "default";
160*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm1>;
161*4882a593Smuzhiyun	status = "okay";
162*4882a593Smuzhiyun};
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun&pwm2 {
165*4882a593Smuzhiyun	pinctrl-names = "default";
166*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm2>;
167*4882a593Smuzhiyun	status = "okay";
168*4882a593Smuzhiyun};
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun&pwm3 {
171*4882a593Smuzhiyun	pinctrl-names = "default";
172*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm3>;
173*4882a593Smuzhiyun	status = "okay";
174*4882a593Smuzhiyun};
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun&pwm4 {
177*4882a593Smuzhiyun	pinctrl-names = "default";
178*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm4>;
179*4882a593Smuzhiyun	status = "okay";
180*4882a593Smuzhiyun};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun&uart1 {
183*4882a593Smuzhiyun	pinctrl-names = "default";
184*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
185*4882a593Smuzhiyun	status = "okay";
186*4882a593Smuzhiyun};
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun&uart2 {
189*4882a593Smuzhiyun	pinctrl-names = "default";
190*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
191*4882a593Smuzhiyun	status = "okay";
192*4882a593Smuzhiyun};
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun&uart3 {
195*4882a593Smuzhiyun	pinctrl-names = "default";
196*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart3>;
197*4882a593Smuzhiyun	status = "okay";
198*4882a593Smuzhiyun};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun&uart4 {
201*4882a593Smuzhiyun	pinctrl-names = "default";
202*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart4>;
203*4882a593Smuzhiyun	status = "okay";
204*4882a593Smuzhiyun};
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun&uart5 {
207*4882a593Smuzhiyun	pinctrl-names = "default";
208*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart5>;
209*4882a593Smuzhiyun	status = "okay";
210*4882a593Smuzhiyun};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun&usbh1 {
213*4882a593Smuzhiyun	dr_mode = "host";
214*4882a593Smuzhiyun	disable-over-current;
215*4882a593Smuzhiyun	status = "okay";
216*4882a593Smuzhiyun};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun&usbotg {
219*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg_vbus>;
220*4882a593Smuzhiyun	pinctrl-names = "default";
221*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg>;
222*4882a593Smuzhiyun	dr_mode = "otg";
223*4882a593Smuzhiyun	disable-over-current;
224*4882a593Smuzhiyun	status = "okay";
225*4882a593Smuzhiyun};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun&usdhc2 {
228*4882a593Smuzhiyun	pinctrl-names = "default";
229*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
230*4882a593Smuzhiyun	vmmc-supply = <&reg_3p3v>;
231*4882a593Smuzhiyun	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
232*4882a593Smuzhiyun	wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
233*4882a593Smuzhiyun	status = "okay";
234*4882a593Smuzhiyun};
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun&usdhc3 {
237*4882a593Smuzhiyun	pinctrl-names = "default";
238*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc3>;
239*4882a593Smuzhiyun	vmmc-supply = <&reg_3p3v>;
240*4882a593Smuzhiyun	non-removable;
241*4882a593Smuzhiyun	status = "okay";
242*4882a593Smuzhiyun};
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun&iomuxc {
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun	pinctrl_audmux: audmuxgrp {
247*4882a593Smuzhiyun		fsl,pins = <
248*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
249*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
250*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
251*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
252*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0	/* CAM_MCLK */
253*4882a593Smuzhiyun		>;
254*4882a593Smuzhiyun	};
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun	pinctrl_ecspi1: ecspi1grp {
257*4882a593Smuzhiyun		fsl,pins = <
258*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
259*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
260*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
261*4882a593Smuzhiyun			MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x000b1	/* CS0 */
262*4882a593Smuzhiyun		>;
263*4882a593Smuzhiyun	};
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun	pinctrl_enet: enetgrp {
266*4882a593Smuzhiyun		fsl,pins = <
267*4882a593Smuzhiyun			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
268*4882a593Smuzhiyun			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
269*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
270*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
271*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
272*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
273*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
274*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
275*4882a593Smuzhiyun			/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
276*4882a593Smuzhiyun			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x0a0b1
277*4882a593Smuzhiyun			/* AR8035 pin strapping: IO voltage: pull up */
278*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
279*4882a593Smuzhiyun			/* AR8035 pin strapping: PHYADDR#0: pull down */
280*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x13030
281*4882a593Smuzhiyun			/* AR8035 pin strapping: PHYADDR#1: pull down */
282*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x13030
283*4882a593Smuzhiyun			/* AR8035 pin strapping: MODE#1: pull up */
284*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
285*4882a593Smuzhiyun			/* AR8035 pin strapping: MODE#3: pull up */
286*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
287*4882a593Smuzhiyun			/* AR8035 pin strapping: MODE#0: pull down */
288*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x13030
289*4882a593Smuzhiyun			/* GPIO16 -> AR8035 25MHz */
290*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
291*4882a593Smuzhiyun			/* RGMII_nRST */
292*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x130b0
293*4882a593Smuzhiyun			/* AR8035 interrupt */
294*4882a593Smuzhiyun			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x180b0
295*4882a593Smuzhiyun		>;
296*4882a593Smuzhiyun	};
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun	pinctrl_i2c1: i2c1grp {
299*4882a593Smuzhiyun		fsl,pins = <
300*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA		0x4001b8b1
301*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001b8b1
302*4882a593Smuzhiyun		>;
303*4882a593Smuzhiyun	};
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun	pinctrl_i2c2: i2c2grp {
306*4882a593Smuzhiyun		fsl,pins = <
307*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
308*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
309*4882a593Smuzhiyun		>;
310*4882a593Smuzhiyun	};
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun	pinctrl_i2c3: i2c3grp {
313*4882a593Smuzhiyun		fsl,pins = <
314*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_5__I2C3_SCL		0x4001b8b1
315*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
316*4882a593Smuzhiyun		>;
317*4882a593Smuzhiyun	};
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun	pinctrl_led: ledgrp {
320*4882a593Smuzhiyun		fsl,pins = <
321*4882a593Smuzhiyun			MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x1b0b1	/* LED1 */
322*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D28__GPIO3_IO28		0x1b0b1	/* LED2 */
323*4882a593Smuzhiyun		>;
324*4882a593Smuzhiyun	};
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun	pinctrl_pwm1: pwm1grp {
327*4882a593Smuzhiyun		fsl,pins = <
328*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT8__PWM1_OUT		0x1b0b1
329*4882a593Smuzhiyun		>;
330*4882a593Smuzhiyun	};
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun	pinctrl_pwm2: pwm2grp {
333*4882a593Smuzhiyun		fsl,pins = <
334*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT9__PWM2_OUT		0x1b0b1
335*4882a593Smuzhiyun		>;
336*4882a593Smuzhiyun	};
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun	pinctrl_pwm3: pwm3grp {
339*4882a593Smuzhiyun		fsl,pins = <
340*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
341*4882a593Smuzhiyun		>;
342*4882a593Smuzhiyun	};
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun	pinctrl_pwm4: pwm4grp {
345*4882a593Smuzhiyun		fsl,pins = <
346*4882a593Smuzhiyun			MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
347*4882a593Smuzhiyun		>;
348*4882a593Smuzhiyun	};
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun	pinctrl_uart1: uart1grp {
351*4882a593Smuzhiyun		fsl,pins = <
352*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
353*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
354*4882a593Smuzhiyun		>;
355*4882a593Smuzhiyun	};
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun	pinctrl_uart2: uart2grp {
358*4882a593Smuzhiyun		fsl,pins = <
359*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1
360*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1
361*4882a593Smuzhiyun		>;
362*4882a593Smuzhiyun	};
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun	pinctrl_uart3: uart3grp {
365*4882a593Smuzhiyun		fsl,pins = <
366*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
367*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
368*4882a593Smuzhiyun		>;
369*4882a593Smuzhiyun	};
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun	pinctrl_uart4: uart4grp {
372*4882a593Smuzhiyun		fsl,pins = <
373*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
374*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
375*4882a593Smuzhiyun		>;
376*4882a593Smuzhiyun	};
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun	pinctrl_uart5: uart5grp {
379*4882a593Smuzhiyun		fsl,pins = <
380*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
381*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
382*4882a593Smuzhiyun		>;
383*4882a593Smuzhiyun	};
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun	pinctrl_usbotg: usbotggrp {
386*4882a593Smuzhiyun		fsl,pins = <
387*4882a593Smuzhiyun			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
388*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D21__USB_OTG_OC		0x1b0b0
389*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x000b0	/* USB OTG POWER ENABLE */
390*4882a593Smuzhiyun		>;
391*4882a593Smuzhiyun	};
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun	pinctrl_usdhc2: usdhc2grp {
394*4882a593Smuzhiyun		fsl,pins = <
395*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
396*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
397*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
398*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
399*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
400*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
401*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0	/* CD */
402*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x1f0b0	/* WP */
403*4882a593Smuzhiyun		>;
404*4882a593Smuzhiyun	};
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun	pinctrl_usdhc3: usdhc3grp {
407*4882a593Smuzhiyun		fsl,pins = <
408*4882a593Smuzhiyun			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17009
409*4882a593Smuzhiyun			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10009
410*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17009
411*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17009
412*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17009
413*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17009
414*4882a593Smuzhiyun			MX6QDL_PAD_SD3_RST__SD3_RESET		0x17009
415*4882a593Smuzhiyun		>;
416*4882a593Smuzhiyun	};
417*4882a593Smuzhiyun};
418