xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * support for the imx6 based aristainetos2 board
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is dual-licensed: you can use it either under the terms
7*4882a593Smuzhiyun * of the GPL or the X11 license, at your option. Note that this dual
8*4882a593Smuzhiyun * licensing only applies to this file, and not this project as a
9*4882a593Smuzhiyun * whole.
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun *  a) This file is free software; you can redistribute it and/or
12*4882a593Smuzhiyun *     modify it under the terms of the GNU General Public License
13*4882a593Smuzhiyun *     version 2 as published by the Free Software Foundation.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun *     This file is distributed in the hope that it will be useful,
16*4882a593Smuzhiyun *     but WITHOUT ANY WARRANTY; without even the implied warranty of
17*4882a593Smuzhiyun *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18*4882a593Smuzhiyun *     GNU General Public License for more details.
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * Or, alternatively,
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun *  b) Permission is hereby granted, free of charge, to any person
23*4882a593Smuzhiyun *     obtaining a copy of this software and associated documentation
24*4882a593Smuzhiyun *     files (the "Software"), to deal in the Software without
25*4882a593Smuzhiyun *     restriction, including without limitation the rights to use,
26*4882a593Smuzhiyun *     copy, modify, merge, publish, distribute, sublicense, and/or
27*4882a593Smuzhiyun *     sell copies of the Software, and to permit persons to whom the
28*4882a593Smuzhiyun *     Software is furnished to do so, subject to the following
29*4882a593Smuzhiyun *     conditions:
30*4882a593Smuzhiyun *
31*4882a593Smuzhiyun *     The above copyright notice and this permission notice shall be
32*4882a593Smuzhiyun *     included in all copies or substantial portions of the Software.
33*4882a593Smuzhiyun *
34*4882a593Smuzhiyun *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35*4882a593Smuzhiyun *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36*4882a593Smuzhiyun *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37*4882a593Smuzhiyun *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38*4882a593Smuzhiyun *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39*4882a593Smuzhiyun *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40*4882a593Smuzhiyun *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41*4882a593Smuzhiyun *     OTHER DEALINGS IN THE SOFTWARE.
42*4882a593Smuzhiyun */
43*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
44*4882a593Smuzhiyun#include <dt-bindings/clock/imx6qdl-clock.h>
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun/ {
47*4882a593Smuzhiyun	backlight: backlight {
48*4882a593Smuzhiyun		compatible = "pwm-backlight";
49*4882a593Smuzhiyun		pwms = <&pwm1 0 5000000>;
50*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
51*4882a593Smuzhiyun		default-brightness-level = <7>;
52*4882a593Smuzhiyun		enable-gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>;
53*4882a593Smuzhiyun	};
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun	reg_2p5v: regulator-2p5v {
56*4882a593Smuzhiyun		compatible = "regulator-fixed";
57*4882a593Smuzhiyun		regulator-name = "2P5V";
58*4882a593Smuzhiyun		regulator-min-microvolt = <2500000>;
59*4882a593Smuzhiyun		regulator-max-microvolt = <2500000>;
60*4882a593Smuzhiyun		regulator-always-on;
61*4882a593Smuzhiyun	};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun	reg_3p3v: regulator-3p3v {
64*4882a593Smuzhiyun		compatible = "regulator-fixed";
65*4882a593Smuzhiyun		regulator-name = "3P3V";
66*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
67*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
68*4882a593Smuzhiyun		regulator-always-on;
69*4882a593Smuzhiyun	};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun	reg_usbh1_vbus: regulator-usbh1-vbus {
72*4882a593Smuzhiyun		compatible = "regulator-fixed";
73*4882a593Smuzhiyun		enable-active-high;
74*4882a593Smuzhiyun		gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
75*4882a593Smuzhiyun		pinctrl-names = "default";
76*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_aristainetos2_usbh1_vbus>;
77*4882a593Smuzhiyun		regulator-name = "usb_h1_vbus";
78*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
79*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
80*4882a593Smuzhiyun	};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun	reg_usbotg_vbus: regulator-usbotg-vbus {
83*4882a593Smuzhiyun		compatible = "regulator-fixed";
84*4882a593Smuzhiyun		enable-active-high;
85*4882a593Smuzhiyun		gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
86*4882a593Smuzhiyun		pinctrl-names = "default";
87*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_aristainetos2_usbotg_vbus>;
88*4882a593Smuzhiyun		regulator-name = "usb_otg_vbus";
89*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
90*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
91*4882a593Smuzhiyun	};
92*4882a593Smuzhiyun};
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun&audmux {
95*4882a593Smuzhiyun	pinctrl-names = "default";
96*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_audmux>;
97*4882a593Smuzhiyun	status = "okay";
98*4882a593Smuzhiyun};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun&can1 {
101*4882a593Smuzhiyun	pinctrl-names = "default";
102*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan1>;
103*4882a593Smuzhiyun	status = "okay";
104*4882a593Smuzhiyun};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun&can2 {
107*4882a593Smuzhiyun	pinctrl-names = "default";
108*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan2>;
109*4882a593Smuzhiyun	status = "okay";
110*4882a593Smuzhiyun};
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun&ecspi1 {
113*4882a593Smuzhiyun	cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW
114*4882a593Smuzhiyun		    &gpio4 10 GPIO_ACTIVE_LOW
115*4882a593Smuzhiyun		    &gpio4 11 GPIO_ACTIVE_LOW>;
116*4882a593Smuzhiyun	pinctrl-names = "default";
117*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
118*4882a593Smuzhiyun	status = "okay";
119*4882a593Smuzhiyun};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun&ecspi2 {
122*4882a593Smuzhiyun	cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW &gpio2 27 GPIO_ACTIVE_LOW>;
123*4882a593Smuzhiyun	pinctrl-names = "default";
124*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi2>;
125*4882a593Smuzhiyun	status = "okay";
126*4882a593Smuzhiyun};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun&ecspi4 {
129*4882a593Smuzhiyun	cs-gpios = <&gpio3 29 GPIO_ACTIVE_LOW &gpio5 2 GPIO_ACTIVE_LOW>;
130*4882a593Smuzhiyun	pinctrl-names = "default";
131*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi4>;
132*4882a593Smuzhiyun	status = "okay";
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun	flash: flash@1 {
135*4882a593Smuzhiyun		#address-cells = <1>;
136*4882a593Smuzhiyun		#size-cells = <1>;
137*4882a593Smuzhiyun		compatible = "micron,n25q128a11", "jedec,spi-nor";
138*4882a593Smuzhiyun		spi-max-frequency = <20000000>;
139*4882a593Smuzhiyun		reg = <1>;
140*4882a593Smuzhiyun	};
141*4882a593Smuzhiyun};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun&i2c1 {
144*4882a593Smuzhiyun	pinctrl-names = "default";
145*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
146*4882a593Smuzhiyun	status = "okay";
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun	pmic@58 {
149*4882a593Smuzhiyun		compatible = "dlg,da9063";
150*4882a593Smuzhiyun		reg = <0x58>;
151*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
152*4882a593Smuzhiyun		interrupts = <04 0x8>;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun		regulators {
155*4882a593Smuzhiyun			bcore1 {
156*4882a593Smuzhiyun				regulator-name = "bcore1";
157*4882a593Smuzhiyun				regulator-always-on = <1>;
158*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
159*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
160*4882a593Smuzhiyun			};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun			bcore2 {
163*4882a593Smuzhiyun				regulator-name = "bcore2";
164*4882a593Smuzhiyun				regulator-always-on = <1>;
165*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
166*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
167*4882a593Smuzhiyun			};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun			bpro {
170*4882a593Smuzhiyun				regulator-name = "bpro";
171*4882a593Smuzhiyun				regulator-always-on = <1>;
172*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
173*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
174*4882a593Smuzhiyun			};
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun			bperi {
177*4882a593Smuzhiyun				regulator-name = "bperi";
178*4882a593Smuzhiyun				regulator-always-on = <1>;
179*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
180*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
181*4882a593Smuzhiyun			};
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun			bmem {
184*4882a593Smuzhiyun				regulator-name = "bmem";
185*4882a593Smuzhiyun				regulator-always-on = <1>;
186*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
187*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
188*4882a593Smuzhiyun			};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun			ldo2 {
191*4882a593Smuzhiyun				regulator-name = "ldo2";
192*4882a593Smuzhiyun				regulator-always-on = <1>;
193*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
194*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
195*4882a593Smuzhiyun			};
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun			ldo3 {
198*4882a593Smuzhiyun				regulator-name = "ldo3";
199*4882a593Smuzhiyun				regulator-always-on = <1>;
200*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
201*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
202*4882a593Smuzhiyun			};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun			ldo4 {
205*4882a593Smuzhiyun				regulator-name = "ldo4";
206*4882a593Smuzhiyun				regulator-always-on = <1>;
207*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
208*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
209*4882a593Smuzhiyun			};
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun			ldo5 {
212*4882a593Smuzhiyun				regulator-name = "ldo5";
213*4882a593Smuzhiyun				regulator-always-on = <1>;
214*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
215*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
216*4882a593Smuzhiyun			};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun			ldo6 {
219*4882a593Smuzhiyun				regulator-name = "ldo6";
220*4882a593Smuzhiyun				regulator-always-on = <1>;
221*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
222*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
223*4882a593Smuzhiyun			};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun			ldo7 {
226*4882a593Smuzhiyun				regulator-name = "ldo7";
227*4882a593Smuzhiyun				regulator-always-on = <1>;
228*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
229*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
230*4882a593Smuzhiyun			};
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun			ldo8 {
233*4882a593Smuzhiyun				regulator-name = "ldo8";
234*4882a593Smuzhiyun				regulator-always-on = <1>;
235*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
236*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
237*4882a593Smuzhiyun			};
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun			ldo9 {
240*4882a593Smuzhiyun				regulator-name = "ldo9";
241*4882a593Smuzhiyun				regulator-always-on = <1>;
242*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
243*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
244*4882a593Smuzhiyun			};
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun			ldo10 {
247*4882a593Smuzhiyun				regulator-name = "ldo10";
248*4882a593Smuzhiyun				regulator-always-on = <1>;
249*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
250*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
251*4882a593Smuzhiyun			};
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun			ldo11 {
254*4882a593Smuzhiyun				regulator-name = "ldo11";
255*4882a593Smuzhiyun				regulator-always-on = <1>;
256*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
257*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
258*4882a593Smuzhiyun			};
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun			bio {
261*4882a593Smuzhiyun				regulator-name = "bio";
262*4882a593Smuzhiyun				regulator-always-on = <1>;
263*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
264*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
265*4882a593Smuzhiyun			};
266*4882a593Smuzhiyun		};
267*4882a593Smuzhiyun	};
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun	tmp103: tmp103@71 {
270*4882a593Smuzhiyun		compatible = "ti,tmp103";
271*4882a593Smuzhiyun		reg = <0x71>;
272*4882a593Smuzhiyun	};
273*4882a593Smuzhiyun};
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun&i2c2 {
276*4882a593Smuzhiyun	pinctrl-names = "default";
277*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
278*4882a593Smuzhiyun	status = "okay";
279*4882a593Smuzhiyun};
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun&i2c3 {
282*4882a593Smuzhiyun	pinctrl-names = "default";
283*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c3>;
284*4882a593Smuzhiyun	status = "okay";
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun	expander: tca6416@20 {
287*4882a593Smuzhiyun		compatible = "ti,tca6416";
288*4882a593Smuzhiyun		reg = <0x20>;
289*4882a593Smuzhiyun		#gpio-cells = <2>;
290*4882a593Smuzhiyun		gpio-controller;
291*4882a593Smuzhiyun	};
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun	rtc@68 {
294*4882a593Smuzhiyun		compatible = "dallas,m41t00";
295*4882a593Smuzhiyun		reg = <0x68>;
296*4882a593Smuzhiyun	};
297*4882a593Smuzhiyun};
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun&i2c4 {
300*4882a593Smuzhiyun	pinctrl-names = "default";
301*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c4>;
302*4882a593Smuzhiyun	status = "okay";
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun	eeprom@50{
305*4882a593Smuzhiyun		compatible = "atmel,24c64";
306*4882a593Smuzhiyun		reg = <0x50>;
307*4882a593Smuzhiyun	};
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun	eeprom@57{
310*4882a593Smuzhiyun		compatible = "atmel,24c64";
311*4882a593Smuzhiyun		reg = <0x57>;
312*4882a593Smuzhiyun	};
313*4882a593Smuzhiyun};
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun&fec {
316*4882a593Smuzhiyun	pinctrl-names = "default";
317*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet>;
318*4882a593Smuzhiyun	phy-mode = "rgmii";
319*4882a593Smuzhiyun	phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_LOW>;
320*4882a593Smuzhiyun	txd0-skew-ps = <0>;
321*4882a593Smuzhiyun	txd1-skew-ps = <0>;
322*4882a593Smuzhiyun	txd2-skew-ps = <0>;
323*4882a593Smuzhiyun	txd3-skew-ps = <0>;
324*4882a593Smuzhiyun	status = "okay";
325*4882a593Smuzhiyun};
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun&gpmi {
328*4882a593Smuzhiyun	pinctrl-names = "default";
329*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_gpmi_nand>;
330*4882a593Smuzhiyun	status = "okay";
331*4882a593Smuzhiyun};
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun&pcie {
334*4882a593Smuzhiyun	reset-gpio = <&gpio2 16 GPIO_ACTIVE_LOW>;
335*4882a593Smuzhiyun	status = "okay";
336*4882a593Smuzhiyun};
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun&pwm1 {
339*4882a593Smuzhiyun	#pwm-cells = <2>;
340*4882a593Smuzhiyun	pinctrl-names = "default";
341*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm1>;
342*4882a593Smuzhiyun	status = "okay";
343*4882a593Smuzhiyun};
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun&uart1 {
346*4882a593Smuzhiyun	pinctrl-names = "default";
347*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
348*4882a593Smuzhiyun	uart-has-rtscts;
349*4882a593Smuzhiyun	status = "okay";
350*4882a593Smuzhiyun};
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun&uart2 {
353*4882a593Smuzhiyun	pinctrl-names = "default";
354*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
355*4882a593Smuzhiyun	status = "okay";
356*4882a593Smuzhiyun};
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun&uart3 {
359*4882a593Smuzhiyun	pinctrl-names = "default";
360*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart3>;
361*4882a593Smuzhiyun	uart-has-rtscts;
362*4882a593Smuzhiyun	status = "okay";
363*4882a593Smuzhiyun};
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun&uart4 {
366*4882a593Smuzhiyun	pinctrl-names = "default";
367*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart4>;
368*4882a593Smuzhiyun	status = "okay";
369*4882a593Smuzhiyun};
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun&usbh1 {
372*4882a593Smuzhiyun	vbus-supply = <&reg_usbh1_vbus>;
373*4882a593Smuzhiyun	dr_mode = "host";
374*4882a593Smuzhiyun	status = "okay";
375*4882a593Smuzhiyun};
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun&usbotg {
378*4882a593Smuzhiyun	vbus-supply = <&reg_usbotg_vbus>;
379*4882a593Smuzhiyun	pinctrl-names = "default";
380*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg>;
381*4882a593Smuzhiyun	disable-over-current;
382*4882a593Smuzhiyun	dr_mode = "host";
383*4882a593Smuzhiyun	status = "okay";
384*4882a593Smuzhiyun};
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun&usdhc1 {
387*4882a593Smuzhiyun	pinctrl-names = "default";
388*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc1>;
389*4882a593Smuzhiyun	cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
390*4882a593Smuzhiyun	no-1-8-v;
391*4882a593Smuzhiyun	status = "okay";
392*4882a593Smuzhiyun};
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun&usdhc2 {
395*4882a593Smuzhiyun	pinctrl-names = "default";
396*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
397*4882a593Smuzhiyun	cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
398*4882a593Smuzhiyun	wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
399*4882a593Smuzhiyun	no-1-8-v;
400*4882a593Smuzhiyun	status = "okay";
401*4882a593Smuzhiyun};
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun&iomuxc {
404*4882a593Smuzhiyun	pinctrl-names = "default";
405*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_gpio>;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun	pinctrl_audmux: audmux {
408*4882a593Smuzhiyun		fsl,pins = <
409*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD  0x1b0b0
410*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC  0x1b0b0
411*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD  0x1b0b0
412*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
413*4882a593Smuzhiyun		>;
414*4882a593Smuzhiyun	};
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun	pinctrl_ecspi1: ecspi1grp {
417*4882a593Smuzhiyun		fsl,pins = <
418*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
419*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
420*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
421*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */
422*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */
423*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */
424*4882a593Smuzhiyun		>;
425*4882a593Smuzhiyun	};
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun	pinctrl_ecspi2: ecspi2grp {
428*4882a593Smuzhiyun		fsl,pins = <
429*4882a593Smuzhiyun			MX6QDL_PAD_EIM_OE__ECSPI2_MISO  0x100b1
430*4882a593Smuzhiyun			MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
431*4882a593Smuzhiyun			MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
432*4882a593Smuzhiyun			MX6QDL_PAD_EIM_RW__GPIO2_IO26   0x100b1 /* SS0# */
433*4882a593Smuzhiyun			MX6QDL_PAD_EIM_LBA__GPIO2_IO27  0x100b1 /* SS1# */
434*4882a593Smuzhiyun		>;
435*4882a593Smuzhiyun	};
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun	pinctrl_ecspi4: ecspi4grp {
438*4882a593Smuzhiyun		fsl,pins = <
439*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
440*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
441*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
442*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D29__GPIO3_IO29  0x100b1 /* SS0# */
443*4882a593Smuzhiyun			MX6QDL_PAD_EIM_A25__GPIO5_IO02  0x100b1 /* SS1# */
444*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */
445*4882a593Smuzhiyun		>;
446*4882a593Smuzhiyun	};
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun	pinctrl_enet: enetgrp {
449*4882a593Smuzhiyun		fsl,pins = <
450*4882a593Smuzhiyun			MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
451*4882a593Smuzhiyun			MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
452*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
453*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
454*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
455*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
456*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
457*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
458*4882a593Smuzhiyun			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
459*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
460*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
461*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
462*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
463*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
464*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
465*4882a593Smuzhiyun		>;
466*4882a593Smuzhiyun	};
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun	pinctrl_flexcan1: flexcan1grp {
469*4882a593Smuzhiyun		fsl,pins = <
470*4882a593Smuzhiyun			MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0
471*4882a593Smuzhiyun			MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0
472*4882a593Smuzhiyun		>;
473*4882a593Smuzhiyun	};
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun	pinctrl_flexcan2: flexcan2grp {
476*4882a593Smuzhiyun		fsl,pins = <
477*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
478*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
479*4882a593Smuzhiyun		>;
480*4882a593Smuzhiyun	};
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun	pinctrl_gpio: gpiogrp {
483*4882a593Smuzhiyun		fsl,pins = <
484*4882a593Smuzhiyun			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x1b0b0 /* led enable */
485*4882a593Smuzhiyun			MX6QDL_PAD_NANDF_CS2__GPIO6_IO15	0x1b0b0 /* LCD power enable */
486*4882a593Smuzhiyun			MX6QDL_PAD_NANDF_CS3__GPIO6_IO16	0x1b0b0 /* led yellow */
487*4882a593Smuzhiyun			MX6QDL_PAD_EIM_EB0__GPIO2_IO28		0x1b0b0 /* led red */
488*4882a593Smuzhiyun			MX6QDL_PAD_EIM_A24__GPIO5_IO04		0x1b0b0 /* led green */
489*4882a593Smuzhiyun			MX6QDL_PAD_EIM_EB1__GPIO2_IO29		0x1b0b0 /* led blue */
490*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x1b0b0 /* Profibus IRQ */
491*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT6__GPIO6_IO18		0x1b0b0 /* FPGA IRQ */
492*4882a593Smuzhiyun			MX6QDL_PAD_EIM_A23__GPIO6_IO06		0x1b0b0 /* spi bus #2 SS driver enable */
493*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x1b0b0 /* RST_LOC# PHY reset input (has pull-down!)*/
494*4882a593Smuzhiyun			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x1b0b0 /* USB_OTG_ID = GPIO1_24*/
495*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT1__GPIO2_IO09		0x1b0b0 /* Touchscreen IRQ */
496*4882a593Smuzhiyun			MX6QDL_PAD_EIM_A22__GPIO2_IO16		0x1b0b0 /* PCIe reset */
497*4882a593Smuzhiyun		>;
498*4882a593Smuzhiyun	};
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun	pinctrl_gpmi_nand: gpmi-nand {
501*4882a593Smuzhiyun		fsl,pins = <
502*4882a593Smuzhiyun			MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
503*4882a593Smuzhiyun			MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
504*4882a593Smuzhiyun			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
505*4882a593Smuzhiyun			MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
506*4882a593Smuzhiyun			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
507*4882a593Smuzhiyun			MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
508*4882a593Smuzhiyun			MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
509*4882a593Smuzhiyun			MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
510*4882a593Smuzhiyun			MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
511*4882a593Smuzhiyun			MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
512*4882a593Smuzhiyun			MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
513*4882a593Smuzhiyun			MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
514*4882a593Smuzhiyun			MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
515*4882a593Smuzhiyun			MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
516*4882a593Smuzhiyun			MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
517*4882a593Smuzhiyun		>;
518*4882a593Smuzhiyun	};
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun	pinctrl_i2c1: i2c1grp {
521*4882a593Smuzhiyun		fsl,pins = <
522*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
523*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
524*4882a593Smuzhiyun		>;
525*4882a593Smuzhiyun	};
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun	pinctrl_i2c2: i2c2grp {
528*4882a593Smuzhiyun		fsl,pins = <
529*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
530*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
531*4882a593Smuzhiyun		>;
532*4882a593Smuzhiyun	};
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun	pinctrl_i2c3: i2c3grp {
535*4882a593Smuzhiyun		fsl,pins = <
536*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
537*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
538*4882a593Smuzhiyun		>;
539*4882a593Smuzhiyun	};
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun	pinctrl_i2c4: i2c4grp {
542*4882a593Smuzhiyun		fsl,pins = <
543*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
544*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
545*4882a593Smuzhiyun		>;
546*4882a593Smuzhiyun	};
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun	pinctrl_pwm1: pwm1grp {
549*4882a593Smuzhiyun		fsl,pins = <
550*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_9__PWM1_OUT	0x1b0b0
551*4882a593Smuzhiyun			MX6QDL_PAD_EIM_BCLK__GPIO6_IO31	0x1b0b0 /* backlight enable */
552*4882a593Smuzhiyun		>;
553*4882a593Smuzhiyun	};
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun	pinctrl_uart1: uart1grp {
556*4882a593Smuzhiyun		fsl,pins = <
557*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
558*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
559*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D20__UART1_RTS_B		0x1b0b1
560*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D19__UART1_CTS_B		0x1b0b1
561*4882a593Smuzhiyun		>;
562*4882a593Smuzhiyun	};
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun	pinctrl_uart2: uart2grp {
565*4882a593Smuzhiyun		fsl,pins = <
566*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
567*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
568*4882a593Smuzhiyun		>;
569*4882a593Smuzhiyun	};
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun	pinctrl_uart3: uart3grp {
572*4882a593Smuzhiyun		fsl,pins = <
573*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
574*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
575*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D31__UART3_RTS_B	  0x1b0b1
576*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D23__UART3_CTS_B	  0x1b0b1
577*4882a593Smuzhiyun		>;
578*4882a593Smuzhiyun	};
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun	pinctrl_uart4: uart4grp {
581*4882a593Smuzhiyun		fsl,pins = <
582*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
583*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
584*4882a593Smuzhiyun		>;
585*4882a593Smuzhiyun	};
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun	pinctrl_usbotg: usbotggrp {
588*4882a593Smuzhiyun		fsl,pins = <
589*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
590*4882a593Smuzhiyun		>;
591*4882a593Smuzhiyun	};
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun	pinctrl_aristainetos2_usbh1_vbus: aristainetos-usbh1-vbus {
594*4882a593Smuzhiyun		fsl,pins = <MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x130b0>;
595*4882a593Smuzhiyun	};
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun	pinctrl_aristainetos2_usbotg_vbus: aristainetos-usbotg-vbus {
598*4882a593Smuzhiyun		fsl,pins = <MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0>;
599*4882a593Smuzhiyun	};
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun	pinctrl_usdhc1: usdhc1grp {
602*4882a593Smuzhiyun		fsl,pins = <
603*4882a593Smuzhiyun			MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
604*4882a593Smuzhiyun			MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
605*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
606*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
607*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
608*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
609*4882a593Smuzhiyun			MX6QDL_PAD_ENET_RXD0__GPIO1_IO27	0x1b0b0 /* SD1 card detect input */
610*4882a593Smuzhiyun			MX6QDL_PAD_DI0_PIN4__GPIO4_IO20		0x1b0b0 /* SD1 write protect input */
611*4882a593Smuzhiyun		>;
612*4882a593Smuzhiyun	};
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun	pinctrl_usdhc2: usdhc2grp {
615*4882a593Smuzhiyun		fsl,pins = <
616*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CMD__SD2_CMD    0x71
617*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CLK__SD2_CLK    0x71
618*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71
619*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71
620*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71
621*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71
622*4882a593Smuzhiyun			MX6QDL_PAD_SD3_RST__GPIO7_IO08		0x1b0b0 /* SD2 level shifter output enable */
623*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_19__GPIO4_IO05		0x1b0b0 /* SD2 card detect input */
624*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT2__GPIO2_IO10		0x1b0b0 /* SD2 write protect input */
625*4882a593Smuzhiyun		>;
626*4882a593Smuzhiyun	};
627*4882a593Smuzhiyun};
628