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Searched refs:CLK_SCLK_MMC0 (Results 1 – 22 of 22) sorted by relevance

/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dexynos5410.h26 #define CLK_SCLK_MMC0 132 macro
H A Dexynos5250.h35 #define CLK_SCLK_MMC0 139 macro
H A Dexynos7-clk.h61 #define CLK_SCLK_MMC0 8 macro
H A Dexynos4.h58 #define CLK_SCLK_MMC0 145 macro
H A Dexynos5420.h33 #define CLK_SCLK_MMC0 132 macro
H A Dexynos3250.h249 #define CLK_SCLK_MMC0 241 macro
H A Dexynos5433.h570 #define CLK_SCLK_MMC0 63 macro
/OK3568_Linux_fs/u-boot/include/dt-bindings/clock/
H A Dexynos7420-clk.h64 #define CLK_SCLK_MMC0 8 macro
/OK3568_Linux_fs/kernel/drivers/clk/samsung/
H A Dclk-exynos5410.c172 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
H A Dclk-exynos5250.c475 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
H A Dclk-exynos3250.c550 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
H A Dclk-exynos7.c534 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
H A Dclk-exynos4.c767 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
H A Dclk-exynos5420.c1006 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
H A Dclk-exynos5433.c2319 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dexynos5410.dtsi132 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
H A Dexynos3250.dtsi371 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
H A Dexynos4.dtsi323 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
H A Dexynos5250.dtsi538 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
H A Dexynos5420.dtsi210 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/exynos/
H A Dexynos7.dtsi526 <&clock_top1 CLK_SCLK_MMC0>;
H A Dexynos5433.dtsi1723 <&cmu_fsys CLK_SCLK_MMC0>;