1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4*4882a593Smuzhiyun * Author: Andrzej Hajda <a.hajda@samsung.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Device Tree binding constants for Exynos5250 clock controller. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H 10*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_EXYNOS_5250_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* core clocks */ 13*4882a593Smuzhiyun #define CLK_FIN_PLL 1 14*4882a593Smuzhiyun #define CLK_FOUT_APLL 2 15*4882a593Smuzhiyun #define CLK_FOUT_MPLL 3 16*4882a593Smuzhiyun #define CLK_FOUT_BPLL 4 17*4882a593Smuzhiyun #define CLK_FOUT_GPLL 5 18*4882a593Smuzhiyun #define CLK_FOUT_CPLL 6 19*4882a593Smuzhiyun #define CLK_FOUT_EPLL 7 20*4882a593Smuzhiyun #define CLK_FOUT_VPLL 8 21*4882a593Smuzhiyun #define CLK_ARM_CLK 9 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* gate for special clocks (sclk) */ 24*4882a593Smuzhiyun #define CLK_SCLK_CAM_BAYER 128 25*4882a593Smuzhiyun #define CLK_SCLK_CAM0 129 26*4882a593Smuzhiyun #define CLK_SCLK_CAM1 130 27*4882a593Smuzhiyun #define CLK_SCLK_GSCL_WA 131 28*4882a593Smuzhiyun #define CLK_SCLK_GSCL_WB 132 29*4882a593Smuzhiyun #define CLK_SCLK_FIMD1 133 30*4882a593Smuzhiyun #define CLK_SCLK_MIPI1 134 31*4882a593Smuzhiyun #define CLK_SCLK_DP 135 32*4882a593Smuzhiyun #define CLK_SCLK_HDMI 136 33*4882a593Smuzhiyun #define CLK_SCLK_PIXEL 137 34*4882a593Smuzhiyun #define CLK_SCLK_AUDIO0 138 35*4882a593Smuzhiyun #define CLK_SCLK_MMC0 139 36*4882a593Smuzhiyun #define CLK_SCLK_MMC1 140 37*4882a593Smuzhiyun #define CLK_SCLK_MMC2 141 38*4882a593Smuzhiyun #define CLK_SCLK_MMC3 142 39*4882a593Smuzhiyun #define CLK_SCLK_SATA 143 40*4882a593Smuzhiyun #define CLK_SCLK_USB3 144 41*4882a593Smuzhiyun #define CLK_SCLK_JPEG 145 42*4882a593Smuzhiyun #define CLK_SCLK_UART0 146 43*4882a593Smuzhiyun #define CLK_SCLK_UART1 147 44*4882a593Smuzhiyun #define CLK_SCLK_UART2 148 45*4882a593Smuzhiyun #define CLK_SCLK_UART3 149 46*4882a593Smuzhiyun #define CLK_SCLK_PWM 150 47*4882a593Smuzhiyun #define CLK_SCLK_AUDIO1 151 48*4882a593Smuzhiyun #define CLK_SCLK_AUDIO2 152 49*4882a593Smuzhiyun #define CLK_SCLK_SPDIF 153 50*4882a593Smuzhiyun #define CLK_SCLK_SPI0 154 51*4882a593Smuzhiyun #define CLK_SCLK_SPI1 155 52*4882a593Smuzhiyun #define CLK_SCLK_SPI2 156 53*4882a593Smuzhiyun #define CLK_DIV_I2S1 157 54*4882a593Smuzhiyun #define CLK_DIV_I2S2 158 55*4882a593Smuzhiyun #define CLK_SCLK_HDMIPHY 159 56*4882a593Smuzhiyun #define CLK_DIV_PCM0 160 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* gate clocks */ 59*4882a593Smuzhiyun #define CLK_GSCL0 256 60*4882a593Smuzhiyun #define CLK_GSCL1 257 61*4882a593Smuzhiyun #define CLK_GSCL2 258 62*4882a593Smuzhiyun #define CLK_GSCL3 259 63*4882a593Smuzhiyun #define CLK_GSCL_WA 260 64*4882a593Smuzhiyun #define CLK_GSCL_WB 261 65*4882a593Smuzhiyun #define CLK_SMMU_GSCL0 262 66*4882a593Smuzhiyun #define CLK_SMMU_GSCL1 263 67*4882a593Smuzhiyun #define CLK_SMMU_GSCL2 264 68*4882a593Smuzhiyun #define CLK_SMMU_GSCL3 265 69*4882a593Smuzhiyun #define CLK_MFC 266 70*4882a593Smuzhiyun #define CLK_SMMU_MFCL 267 71*4882a593Smuzhiyun #define CLK_SMMU_MFCR 268 72*4882a593Smuzhiyun #define CLK_ROTATOR 269 73*4882a593Smuzhiyun #define CLK_JPEG 270 74*4882a593Smuzhiyun #define CLK_MDMA1 271 75*4882a593Smuzhiyun #define CLK_SMMU_ROTATOR 272 76*4882a593Smuzhiyun #define CLK_SMMU_JPEG 273 77*4882a593Smuzhiyun #define CLK_SMMU_MDMA1 274 78*4882a593Smuzhiyun #define CLK_PDMA0 275 79*4882a593Smuzhiyun #define CLK_PDMA1 276 80*4882a593Smuzhiyun #define CLK_SATA 277 81*4882a593Smuzhiyun #define CLK_USBOTG 278 82*4882a593Smuzhiyun #define CLK_MIPI_HSI 279 83*4882a593Smuzhiyun #define CLK_SDMMC0 280 84*4882a593Smuzhiyun #define CLK_SDMMC1 281 85*4882a593Smuzhiyun #define CLK_SDMMC2 282 86*4882a593Smuzhiyun #define CLK_SDMMC3 283 87*4882a593Smuzhiyun #define CLK_SROMC 284 88*4882a593Smuzhiyun #define CLK_USB2 285 89*4882a593Smuzhiyun #define CLK_USB3 286 90*4882a593Smuzhiyun #define CLK_SATA_PHYCTRL 287 91*4882a593Smuzhiyun #define CLK_SATA_PHYI2C 288 92*4882a593Smuzhiyun #define CLK_UART0 289 93*4882a593Smuzhiyun #define CLK_UART1 290 94*4882a593Smuzhiyun #define CLK_UART2 291 95*4882a593Smuzhiyun #define CLK_UART3 292 96*4882a593Smuzhiyun #define CLK_UART4 293 97*4882a593Smuzhiyun #define CLK_I2C0 294 98*4882a593Smuzhiyun #define CLK_I2C1 295 99*4882a593Smuzhiyun #define CLK_I2C2 296 100*4882a593Smuzhiyun #define CLK_I2C3 297 101*4882a593Smuzhiyun #define CLK_I2C4 298 102*4882a593Smuzhiyun #define CLK_I2C5 299 103*4882a593Smuzhiyun #define CLK_I2C6 300 104*4882a593Smuzhiyun #define CLK_I2C7 301 105*4882a593Smuzhiyun #define CLK_I2C_HDMI 302 106*4882a593Smuzhiyun #define CLK_ADC 303 107*4882a593Smuzhiyun #define CLK_SPI0 304 108*4882a593Smuzhiyun #define CLK_SPI1 305 109*4882a593Smuzhiyun #define CLK_SPI2 306 110*4882a593Smuzhiyun #define CLK_I2S1 307 111*4882a593Smuzhiyun #define CLK_I2S2 308 112*4882a593Smuzhiyun #define CLK_PCM1 309 113*4882a593Smuzhiyun #define CLK_PCM2 310 114*4882a593Smuzhiyun #define CLK_PWM 311 115*4882a593Smuzhiyun #define CLK_SPDIF 312 116*4882a593Smuzhiyun #define CLK_AC97 313 117*4882a593Smuzhiyun #define CLK_HSI2C0 314 118*4882a593Smuzhiyun #define CLK_HSI2C1 315 119*4882a593Smuzhiyun #define CLK_HSI2C2 316 120*4882a593Smuzhiyun #define CLK_HSI2C3 317 121*4882a593Smuzhiyun #define CLK_CHIPID 318 122*4882a593Smuzhiyun #define CLK_SYSREG 319 123*4882a593Smuzhiyun #define CLK_PMU 320 124*4882a593Smuzhiyun #define CLK_CMU_TOP 321 125*4882a593Smuzhiyun #define CLK_CMU_CORE 322 126*4882a593Smuzhiyun #define CLK_CMU_MEM 323 127*4882a593Smuzhiyun #define CLK_TZPC0 324 128*4882a593Smuzhiyun #define CLK_TZPC1 325 129*4882a593Smuzhiyun #define CLK_TZPC2 326 130*4882a593Smuzhiyun #define CLK_TZPC3 327 131*4882a593Smuzhiyun #define CLK_TZPC4 328 132*4882a593Smuzhiyun #define CLK_TZPC5 329 133*4882a593Smuzhiyun #define CLK_TZPC6 330 134*4882a593Smuzhiyun #define CLK_TZPC7 331 135*4882a593Smuzhiyun #define CLK_TZPC8 332 136*4882a593Smuzhiyun #define CLK_TZPC9 333 137*4882a593Smuzhiyun #define CLK_HDMI_CEC 334 138*4882a593Smuzhiyun #define CLK_MCT 335 139*4882a593Smuzhiyun #define CLK_WDT 336 140*4882a593Smuzhiyun #define CLK_RTC 337 141*4882a593Smuzhiyun #define CLK_TMU 338 142*4882a593Smuzhiyun #define CLK_FIMD1 339 143*4882a593Smuzhiyun #define CLK_MIE1 340 144*4882a593Smuzhiyun #define CLK_DSIM0 341 145*4882a593Smuzhiyun #define CLK_DP 342 146*4882a593Smuzhiyun #define CLK_MIXER 343 147*4882a593Smuzhiyun #define CLK_HDMI 344 148*4882a593Smuzhiyun #define CLK_G2D 345 149*4882a593Smuzhiyun #define CLK_MDMA0 346 150*4882a593Smuzhiyun #define CLK_SMMU_MDMA0 347 151*4882a593Smuzhiyun #define CLK_SSS 348 152*4882a593Smuzhiyun #define CLK_G3D 349 153*4882a593Smuzhiyun #define CLK_SMMU_TV 350 154*4882a593Smuzhiyun #define CLK_SMMU_FIMD1 351 155*4882a593Smuzhiyun #define CLK_SMMU_2D 352 156*4882a593Smuzhiyun #define CLK_SMMU_FIMC_ISP 353 157*4882a593Smuzhiyun #define CLK_SMMU_FIMC_DRC 354 158*4882a593Smuzhiyun #define CLK_SMMU_FIMC_SCC 355 159*4882a593Smuzhiyun #define CLK_SMMU_FIMC_SCP 356 160*4882a593Smuzhiyun #define CLK_SMMU_FIMC_FD 357 161*4882a593Smuzhiyun #define CLK_SMMU_FIMC_MCU 358 162*4882a593Smuzhiyun #define CLK_SMMU_FIMC_ODC 359 163*4882a593Smuzhiyun #define CLK_SMMU_FIMC_DIS0 360 164*4882a593Smuzhiyun #define CLK_SMMU_FIMC_DIS1 361 165*4882a593Smuzhiyun #define CLK_SMMU_FIMC_3DNR 362 166*4882a593Smuzhiyun #define CLK_SMMU_FIMC_LITE0 363 167*4882a593Smuzhiyun #define CLK_SMMU_FIMC_LITE1 364 168*4882a593Smuzhiyun #define CLK_CAMIF_TOP 365 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun /* mux clocks */ 171*4882a593Smuzhiyun #define CLK_MOUT_HDMI 1024 172*4882a593Smuzhiyun #define CLK_MOUT_GPLL 1025 173*4882a593Smuzhiyun #define CLK_MOUT_ACLK200_DISP1_SUB 1026 174*4882a593Smuzhiyun #define CLK_MOUT_ACLK300_DISP1_SUB 1027 175*4882a593Smuzhiyun #define CLK_MOUT_APLL 1028 176*4882a593Smuzhiyun #define CLK_MOUT_MPLL 1029 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun /* must be greater than maximal clock id */ 179*4882a593Smuzhiyun #define CLK_NR_CLKS 1030 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ 182