1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014 Samsung Electronics Co., Ltd. 4*4882a593Smuzhiyun * Copyright (c) 2016 Krzysztof Kozlowski 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Device Tree binding constants for Exynos5421 clock controller. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H 10*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_EXYNOS_5410_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* core clocks */ 13*4882a593Smuzhiyun #define CLK_FIN_PLL 1 14*4882a593Smuzhiyun #define CLK_FOUT_APLL 2 15*4882a593Smuzhiyun #define CLK_FOUT_CPLL 3 16*4882a593Smuzhiyun #define CLK_FOUT_MPLL 4 17*4882a593Smuzhiyun #define CLK_FOUT_BPLL 5 18*4882a593Smuzhiyun #define CLK_FOUT_KPLL 6 19*4882a593Smuzhiyun #define CLK_FOUT_EPLL 7 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* gate for special clocks (sclk) */ 22*4882a593Smuzhiyun #define CLK_SCLK_UART0 128 23*4882a593Smuzhiyun #define CLK_SCLK_UART1 129 24*4882a593Smuzhiyun #define CLK_SCLK_UART2 130 25*4882a593Smuzhiyun #define CLK_SCLK_UART3 131 26*4882a593Smuzhiyun #define CLK_SCLK_MMC0 132 27*4882a593Smuzhiyun #define CLK_SCLK_MMC1 133 28*4882a593Smuzhiyun #define CLK_SCLK_MMC2 134 29*4882a593Smuzhiyun #define CLK_SCLK_USBD300 150 30*4882a593Smuzhiyun #define CLK_SCLK_USBD301 151 31*4882a593Smuzhiyun #define CLK_SCLK_USBPHY300 152 32*4882a593Smuzhiyun #define CLK_SCLK_USBPHY301 153 33*4882a593Smuzhiyun #define CLK_SCLK_PWM 155 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* gate clocks */ 36*4882a593Smuzhiyun #define CLK_UART0 257 37*4882a593Smuzhiyun #define CLK_UART1 258 38*4882a593Smuzhiyun #define CLK_UART2 259 39*4882a593Smuzhiyun #define CLK_UART3 260 40*4882a593Smuzhiyun #define CLK_I2C0 261 41*4882a593Smuzhiyun #define CLK_I2C1 262 42*4882a593Smuzhiyun #define CLK_I2C2 263 43*4882a593Smuzhiyun #define CLK_I2C3 264 44*4882a593Smuzhiyun #define CLK_USI0 265 45*4882a593Smuzhiyun #define CLK_USI1 266 46*4882a593Smuzhiyun #define CLK_USI2 267 47*4882a593Smuzhiyun #define CLK_USI3 268 48*4882a593Smuzhiyun #define CLK_TSADC 270 49*4882a593Smuzhiyun #define CLK_PWM 279 50*4882a593Smuzhiyun #define CLK_MCT 315 51*4882a593Smuzhiyun #define CLK_WDT 316 52*4882a593Smuzhiyun #define CLK_RTC 317 53*4882a593Smuzhiyun #define CLK_TMU 318 54*4882a593Smuzhiyun #define CLK_MMC0 351 55*4882a593Smuzhiyun #define CLK_MMC1 352 56*4882a593Smuzhiyun #define CLK_MMC2 353 57*4882a593Smuzhiyun #define CLK_PDMA0 362 58*4882a593Smuzhiyun #define CLK_PDMA1 363 59*4882a593Smuzhiyun #define CLK_USBH20 365 60*4882a593Smuzhiyun #define CLK_USBD300 366 61*4882a593Smuzhiyun #define CLK_USBD301 367 62*4882a593Smuzhiyun #define CLK_SSS 471 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define CLK_NR_CLKS 512 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */ 67