1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4*4882a593Smuzhiyun * Author: Andrzej Hajda <a.hajda@samsung.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Device Tree binding constants for Exynos4 clock controller. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H 10*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_EXYNOS_4_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* core clocks */ 13*4882a593Smuzhiyun #define CLK_XXTI 1 14*4882a593Smuzhiyun #define CLK_XUSBXTI 2 15*4882a593Smuzhiyun #define CLK_FIN_PLL 3 16*4882a593Smuzhiyun #define CLK_FOUT_APLL 4 17*4882a593Smuzhiyun #define CLK_FOUT_MPLL 5 18*4882a593Smuzhiyun #define CLK_FOUT_EPLL 6 19*4882a593Smuzhiyun #define CLK_FOUT_VPLL 7 20*4882a593Smuzhiyun #define CLK_SCLK_APLL 8 21*4882a593Smuzhiyun #define CLK_SCLK_MPLL 9 22*4882a593Smuzhiyun #define CLK_SCLK_EPLL 10 23*4882a593Smuzhiyun #define CLK_SCLK_VPLL 11 24*4882a593Smuzhiyun #define CLK_ARM_CLK 12 25*4882a593Smuzhiyun #define CLK_ACLK200 13 26*4882a593Smuzhiyun #define CLK_ACLK100 14 27*4882a593Smuzhiyun #define CLK_ACLK160 15 28*4882a593Smuzhiyun #define CLK_ACLK133 16 29*4882a593Smuzhiyun #define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */ 30*4882a593Smuzhiyun #define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */ 31*4882a593Smuzhiyun #define CLK_MOUT_CORE 19 32*4882a593Smuzhiyun #define CLK_MOUT_APLL 20 33*4882a593Smuzhiyun #define CLK_SCLK_HDMIPHY 22 34*4882a593Smuzhiyun #define CLK_OUT_DMC 23 35*4882a593Smuzhiyun #define CLK_OUT_TOP 24 36*4882a593Smuzhiyun #define CLK_OUT_LEFTBUS 25 37*4882a593Smuzhiyun #define CLK_OUT_RIGHTBUS 26 38*4882a593Smuzhiyun #define CLK_OUT_CPU 27 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* gate for special clocks (sclk) */ 41*4882a593Smuzhiyun #define CLK_SCLK_FIMC0 128 42*4882a593Smuzhiyun #define CLK_SCLK_FIMC1 129 43*4882a593Smuzhiyun #define CLK_SCLK_FIMC2 130 44*4882a593Smuzhiyun #define CLK_SCLK_FIMC3 131 45*4882a593Smuzhiyun #define CLK_SCLK_CAM0 132 46*4882a593Smuzhiyun #define CLK_SCLK_CAM1 133 47*4882a593Smuzhiyun #define CLK_SCLK_CSIS0 134 48*4882a593Smuzhiyun #define CLK_SCLK_CSIS1 135 49*4882a593Smuzhiyun #define CLK_SCLK_HDMI 136 50*4882a593Smuzhiyun #define CLK_SCLK_MIXER 137 51*4882a593Smuzhiyun #define CLK_SCLK_DAC 138 52*4882a593Smuzhiyun #define CLK_SCLK_PIXEL 139 53*4882a593Smuzhiyun #define CLK_SCLK_FIMD0 140 54*4882a593Smuzhiyun #define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */ 55*4882a593Smuzhiyun #define CLK_SCLK_MDNIE_PWM0 142 56*4882a593Smuzhiyun #define CLK_SCLK_MIPI0 143 57*4882a593Smuzhiyun #define CLK_SCLK_AUDIO0 144 58*4882a593Smuzhiyun #define CLK_SCLK_MMC0 145 59*4882a593Smuzhiyun #define CLK_SCLK_MMC1 146 60*4882a593Smuzhiyun #define CLK_SCLK_MMC2 147 61*4882a593Smuzhiyun #define CLK_SCLK_MMC3 148 62*4882a593Smuzhiyun #define CLK_SCLK_MMC4 149 63*4882a593Smuzhiyun #define CLK_SCLK_SATA 150 /* Exynos4210 only */ 64*4882a593Smuzhiyun #define CLK_SCLK_UART0 151 65*4882a593Smuzhiyun #define CLK_SCLK_UART1 152 66*4882a593Smuzhiyun #define CLK_SCLK_UART2 153 67*4882a593Smuzhiyun #define CLK_SCLK_UART3 154 68*4882a593Smuzhiyun #define CLK_SCLK_UART4 155 69*4882a593Smuzhiyun #define CLK_SCLK_AUDIO1 156 70*4882a593Smuzhiyun #define CLK_SCLK_AUDIO2 157 71*4882a593Smuzhiyun #define CLK_SCLK_SPDIF 158 72*4882a593Smuzhiyun #define CLK_SCLK_SPI0 159 73*4882a593Smuzhiyun #define CLK_SCLK_SPI1 160 74*4882a593Smuzhiyun #define CLK_SCLK_SPI2 161 75*4882a593Smuzhiyun #define CLK_SCLK_SLIMBUS 162 76*4882a593Smuzhiyun #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */ 77*4882a593Smuzhiyun #define CLK_SCLK_MIPI1 164 /* Exynos4210 only */ 78*4882a593Smuzhiyun #define CLK_SCLK_PCM1 165 79*4882a593Smuzhiyun #define CLK_SCLK_PCM2 166 80*4882a593Smuzhiyun #define CLK_SCLK_I2S1 167 81*4882a593Smuzhiyun #define CLK_SCLK_I2S2 168 82*4882a593Smuzhiyun #define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */ 83*4882a593Smuzhiyun #define CLK_SCLK_MFC 170 84*4882a593Smuzhiyun #define CLK_SCLK_PCM0 171 85*4882a593Smuzhiyun #define CLK_SCLK_G3D 172 86*4882a593Smuzhiyun #define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */ 87*4882a593Smuzhiyun #define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */ 88*4882a593Smuzhiyun #define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */ 89*4882a593Smuzhiyun #define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */ 90*4882a593Smuzhiyun #define CLK_SCLK_FIMG2D 177 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* gate clocks */ 93*4882a593Smuzhiyun #define CLK_SSS 255 94*4882a593Smuzhiyun #define CLK_FIMC0 256 95*4882a593Smuzhiyun #define CLK_FIMC1 257 96*4882a593Smuzhiyun #define CLK_FIMC2 258 97*4882a593Smuzhiyun #define CLK_FIMC3 259 98*4882a593Smuzhiyun #define CLK_CSIS0 260 99*4882a593Smuzhiyun #define CLK_CSIS1 261 100*4882a593Smuzhiyun #define CLK_JPEG 262 101*4882a593Smuzhiyun #define CLK_SMMU_FIMC0 263 102*4882a593Smuzhiyun #define CLK_SMMU_FIMC1 264 103*4882a593Smuzhiyun #define CLK_SMMU_FIMC2 265 104*4882a593Smuzhiyun #define CLK_SMMU_FIMC3 266 105*4882a593Smuzhiyun #define CLK_SMMU_JPEG 267 106*4882a593Smuzhiyun #define CLK_VP 268 107*4882a593Smuzhiyun #define CLK_MIXER 269 108*4882a593Smuzhiyun #define CLK_TVENC 270 /* Exynos4210 only */ 109*4882a593Smuzhiyun #define CLK_HDMI 271 110*4882a593Smuzhiyun #define CLK_SMMU_TV 272 111*4882a593Smuzhiyun #define CLK_MFC 273 112*4882a593Smuzhiyun #define CLK_SMMU_MFCL 274 113*4882a593Smuzhiyun #define CLK_SMMU_MFCR 275 114*4882a593Smuzhiyun #define CLK_G3D 276 115*4882a593Smuzhiyun #define CLK_G2D 277 116*4882a593Smuzhiyun #define CLK_ROTATOR 278 117*4882a593Smuzhiyun #define CLK_MDMA 279 118*4882a593Smuzhiyun #define CLK_SMMU_G2D 280 119*4882a593Smuzhiyun #define CLK_SMMU_ROTATOR 281 120*4882a593Smuzhiyun #define CLK_SMMU_MDMA 282 121*4882a593Smuzhiyun #define CLK_FIMD0 283 122*4882a593Smuzhiyun #define CLK_MIE0 284 123*4882a593Smuzhiyun #define CLK_MDNIE0 285 /* Exynos4412 only */ 124*4882a593Smuzhiyun #define CLK_DSIM0 286 125*4882a593Smuzhiyun #define CLK_SMMU_FIMD0 287 126*4882a593Smuzhiyun #define CLK_FIMD1 288 /* Exynos4210 only */ 127*4882a593Smuzhiyun #define CLK_MIE1 289 /* Exynos4210 only */ 128*4882a593Smuzhiyun #define CLK_DSIM1 290 /* Exynos4210 only */ 129*4882a593Smuzhiyun #define CLK_SMMU_FIMD1 291 /* Exynos4210 only */ 130*4882a593Smuzhiyun #define CLK_PDMA0 292 131*4882a593Smuzhiyun #define CLK_PDMA1 293 132*4882a593Smuzhiyun #define CLK_PCIE_PHY 294 133*4882a593Smuzhiyun #define CLK_SATA_PHY 295 /* Exynos4210 only */ 134*4882a593Smuzhiyun #define CLK_TSI 296 135*4882a593Smuzhiyun #define CLK_SDMMC0 297 136*4882a593Smuzhiyun #define CLK_SDMMC1 298 137*4882a593Smuzhiyun #define CLK_SDMMC2 299 138*4882a593Smuzhiyun #define CLK_SDMMC3 300 139*4882a593Smuzhiyun #define CLK_SDMMC4 301 140*4882a593Smuzhiyun #define CLK_SATA 302 /* Exynos4210 only */ 141*4882a593Smuzhiyun #define CLK_SROMC 303 142*4882a593Smuzhiyun #define CLK_USB_HOST 304 143*4882a593Smuzhiyun #define CLK_USB_DEVICE 305 144*4882a593Smuzhiyun #define CLK_PCIE 306 145*4882a593Smuzhiyun #define CLK_ONENAND 307 146*4882a593Smuzhiyun #define CLK_NFCON 308 147*4882a593Smuzhiyun #define CLK_SMMU_PCIE 309 148*4882a593Smuzhiyun #define CLK_GPS 310 149*4882a593Smuzhiyun #define CLK_SMMU_GPS 311 150*4882a593Smuzhiyun #define CLK_UART0 312 151*4882a593Smuzhiyun #define CLK_UART1 313 152*4882a593Smuzhiyun #define CLK_UART2 314 153*4882a593Smuzhiyun #define CLK_UART3 315 154*4882a593Smuzhiyun #define CLK_UART4 316 155*4882a593Smuzhiyun #define CLK_I2C0 317 156*4882a593Smuzhiyun #define CLK_I2C1 318 157*4882a593Smuzhiyun #define CLK_I2C2 319 158*4882a593Smuzhiyun #define CLK_I2C3 320 159*4882a593Smuzhiyun #define CLK_I2C4 321 160*4882a593Smuzhiyun #define CLK_I2C5 322 161*4882a593Smuzhiyun #define CLK_I2C6 323 162*4882a593Smuzhiyun #define CLK_I2C7 324 163*4882a593Smuzhiyun #define CLK_I2C_HDMI 325 164*4882a593Smuzhiyun #define CLK_TSADC 326 165*4882a593Smuzhiyun #define CLK_SPI0 327 166*4882a593Smuzhiyun #define CLK_SPI1 328 167*4882a593Smuzhiyun #define CLK_SPI2 329 168*4882a593Smuzhiyun #define CLK_I2S1 330 169*4882a593Smuzhiyun #define CLK_I2S2 331 170*4882a593Smuzhiyun #define CLK_PCM0 332 171*4882a593Smuzhiyun #define CLK_I2S0 333 172*4882a593Smuzhiyun #define CLK_PCM1 334 173*4882a593Smuzhiyun #define CLK_PCM2 335 174*4882a593Smuzhiyun #define CLK_PWM 336 175*4882a593Smuzhiyun #define CLK_SLIMBUS 337 176*4882a593Smuzhiyun #define CLK_SPDIF 338 177*4882a593Smuzhiyun #define CLK_AC97 339 178*4882a593Smuzhiyun #define CLK_MODEMIF 340 179*4882a593Smuzhiyun #define CLK_CHIPID 341 180*4882a593Smuzhiyun #define CLK_SYSREG 342 181*4882a593Smuzhiyun #define CLK_HDMI_CEC 343 182*4882a593Smuzhiyun #define CLK_MCT 344 183*4882a593Smuzhiyun #define CLK_WDT 345 184*4882a593Smuzhiyun #define CLK_RTC 346 185*4882a593Smuzhiyun #define CLK_KEYIF 347 186*4882a593Smuzhiyun #define CLK_AUDSS 348 187*4882a593Smuzhiyun #define CLK_MIPI_HSI 349 /* Exynos4210 only */ 188*4882a593Smuzhiyun #define CLK_PIXELASYNCM0 351 189*4882a593Smuzhiyun #define CLK_PIXELASYNCM1 352 190*4882a593Smuzhiyun #define CLK_ASYNC_G3D 353 /* Exynos4x12 only */ 191*4882a593Smuzhiyun #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ 192*4882a593Smuzhiyun #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ 193*4882a593Smuzhiyun #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */ 194*4882a593Smuzhiyun #define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */ 195*4882a593Smuzhiyun #define CLK_TMU_APBIF 383 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun /* mux clocks */ 198*4882a593Smuzhiyun #define CLK_MOUT_FIMC0 384 199*4882a593Smuzhiyun #define CLK_MOUT_FIMC1 385 200*4882a593Smuzhiyun #define CLK_MOUT_FIMC2 386 201*4882a593Smuzhiyun #define CLK_MOUT_FIMC3 387 202*4882a593Smuzhiyun #define CLK_MOUT_CAM0 388 203*4882a593Smuzhiyun #define CLK_MOUT_CAM1 389 204*4882a593Smuzhiyun #define CLK_MOUT_CSIS0 390 205*4882a593Smuzhiyun #define CLK_MOUT_CSIS1 391 206*4882a593Smuzhiyun #define CLK_MOUT_G3D0 392 207*4882a593Smuzhiyun #define CLK_MOUT_G3D1 393 208*4882a593Smuzhiyun #define CLK_MOUT_G3D 394 209*4882a593Smuzhiyun #define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */ 210*4882a593Smuzhiyun #define CLK_MOUT_HDMI 396 211*4882a593Smuzhiyun #define CLK_MOUT_MIXER 397 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun /* gate clocks - ppmu */ 214*4882a593Smuzhiyun #define CLK_PPMULEFT 400 215*4882a593Smuzhiyun #define CLK_PPMURIGHT 401 216*4882a593Smuzhiyun #define CLK_PPMUCAMIF 402 217*4882a593Smuzhiyun #define CLK_PPMUTV 403 218*4882a593Smuzhiyun #define CLK_PPMUMFC_L 404 219*4882a593Smuzhiyun #define CLK_PPMUMFC_R 405 220*4882a593Smuzhiyun #define CLK_PPMUG3D 406 221*4882a593Smuzhiyun #define CLK_PPMUIMAGE 407 222*4882a593Smuzhiyun #define CLK_PPMULCD0 408 223*4882a593Smuzhiyun #define CLK_PPMULCD1 409 /* Exynos4210 only */ 224*4882a593Smuzhiyun #define CLK_PPMUFILE 410 225*4882a593Smuzhiyun #define CLK_PPMUGPS 411 226*4882a593Smuzhiyun #define CLK_PPMUDMC0 412 227*4882a593Smuzhiyun #define CLK_PPMUDMC1 413 228*4882a593Smuzhiyun #define CLK_PPMUCPU 414 229*4882a593Smuzhiyun #define CLK_PPMUACP 415 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /* div clocks */ 232*4882a593Smuzhiyun #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ 233*4882a593Smuzhiyun #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ 234*4882a593Smuzhiyun #define CLK_DIV_ACP 456 235*4882a593Smuzhiyun #define CLK_DIV_DMC 457 236*4882a593Smuzhiyun #define CLK_DIV_C2C 458 /* Exynos4x12 only */ 237*4882a593Smuzhiyun #define CLK_DIV_GDL 459 238*4882a593Smuzhiyun #define CLK_DIV_GDR 460 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun /* must be greater than maximal clock id */ 241*4882a593Smuzhiyun #define CLK_NR_CLKS 461 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun /* Exynos4x12 ISP clocks */ 244*4882a593Smuzhiyun #define CLK_ISP_FIMC_ISP 1 245*4882a593Smuzhiyun #define CLK_ISP_FIMC_DRC 2 246*4882a593Smuzhiyun #define CLK_ISP_FIMC_FD 3 247*4882a593Smuzhiyun #define CLK_ISP_FIMC_LITE0 4 248*4882a593Smuzhiyun #define CLK_ISP_FIMC_LITE1 5 249*4882a593Smuzhiyun #define CLK_ISP_MCUISP 6 250*4882a593Smuzhiyun #define CLK_ISP_GICISP 7 251*4882a593Smuzhiyun #define CLK_ISP_SMMU_ISP 8 252*4882a593Smuzhiyun #define CLK_ISP_SMMU_DRC 9 253*4882a593Smuzhiyun #define CLK_ISP_SMMU_FD 10 254*4882a593Smuzhiyun #define CLK_ISP_SMMU_LITE0 11 255*4882a593Smuzhiyun #define CLK_ISP_SMMU_LITE1 12 256*4882a593Smuzhiyun #define CLK_ISP_PPMUISPMX 13 257*4882a593Smuzhiyun #define CLK_ISP_PPMUISPX 14 258*4882a593Smuzhiyun #define CLK_ISP_MCUCTL_ISP 15 259*4882a593Smuzhiyun #define CLK_ISP_MPWM_ISP 16 260*4882a593Smuzhiyun #define CLK_ISP_I2C0_ISP 17 261*4882a593Smuzhiyun #define CLK_ISP_I2C1_ISP 18 262*4882a593Smuzhiyun #define CLK_ISP_MTCADC_ISP 19 263*4882a593Smuzhiyun #define CLK_ISP_PWM_ISP 20 264*4882a593Smuzhiyun #define CLK_ISP_WDT_ISP 21 265*4882a593Smuzhiyun #define CLK_ISP_UART_ISP 22 266*4882a593Smuzhiyun #define CLK_ISP_ASYNCAXIM 23 267*4882a593Smuzhiyun #define CLK_ISP_SMMU_ISPCX 24 268*4882a593Smuzhiyun #define CLK_ISP_SPI0_ISP 25 269*4882a593Smuzhiyun #define CLK_ISP_SPI1_ISP 26 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun #define CLK_ISP_DIV_ISP0 27 272*4882a593Smuzhiyun #define CLK_ISP_DIV_ISP1 28 273*4882a593Smuzhiyun #define CLK_ISP_DIV_MCUISP0 29 274*4882a593Smuzhiyun #define CLK_ISP_DIV_MCUISP1 30 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun #define CLK_NR_ISP_CLKS 31 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ 279