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/OK3568_Linux_fs/u-boot/drivers/ddr/fsl/
H A Dmpc85xx_ddr_gen3.c17 * regs has the to-be-set values for DDR controller registers
18 * ctrl_num is the DDR controller number
22 * Dividing the initialization to two steps to deassert DDR reset signal
29 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
45 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
49 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
54 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
59 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_set_memctl_regs()
71 out_be32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
94 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
[all …]
H A Dfsl_ddr_gen4.c41 * regs has the to-be-set values for DDR controller registers
42 * ctrl_num is the DDR controller number
46 * Dividing the initialization to two steps to deassert DDR reset signal
53 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
73 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
77 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
82 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
87 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_set_memctl_regs()
99 ddr_out32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
101 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); in fsl_ddr_set_memctl_regs()
[all …]
H A Darm_ddr_gen3.c23 * regs has the to-be-set values for DDR controller registers
24 * ctrl_num is the DDR controller number
28 * Dividing the initialization to two steps to deassert DDR reset signal
35 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
42 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
46 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
51 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
56 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_set_memctl_regs()
68 ddr_out32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
71 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
[all …]
H A Dmpc86xx_ddr.c19 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
23 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
26 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
35 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
36 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
39 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
40 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
43 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
44 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
47 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
[all …]
H A Dctrl_regs.c8 * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller.
148 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, in set_csn_config() argument
225 ddr->cs[i].config = (0 in set_csn_config()
244 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); in set_csn_config()
249 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) in set_csn_config_2() argument
253 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); in set_csn_config_2()
254 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); in set_csn_config_2()
289 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
291 * Avoid writing for DDR I. The new PQ38 DDR controller
295 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_0() argument
[all …]
H A Dmpc85xx_ddr_gen2.c20 struct ccsr_ddr __iomem *ddr = in fsl_ddr_set_memctl_regs() local
35 * Set the DDR IO receiver to an acceptable bias point. in fsl_ddr_set_memctl_regs()
50 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
51 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
54 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
55 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
58 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
59 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
62 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
63 out_be32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
[all …]
H A Dmpc85xx_ddr_gen1.c19 struct ccsr_ddr __iomem *ddr = in fsl_ddr_set_memctl_regs() local
29 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
30 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
33 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
34 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
37 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
38 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
41 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
42 out_be32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
46 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
[all …]
H A Dutil.c30 struct ccsr_ddr __iomem *ddr; in fsl_ddr_get_version() local
35 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_get_version()
39 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_get_version()
44 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_get_version()
49 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_get_version()
56 ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8; in fsl_ddr_get_version()
57 ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8; in fsl_ddr_get_version()
147 debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n", in __fsl_ddr_set_lawbar()
178 struct ccsr_ddr __iomem *ddr = in print_ddr_info() local
185 uint32_t cs0_config = ddr_in32(&ddr->cs0_config); in print_ddr_info()
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/bsc9132qds/
H A Dspl_minimal.c20 struct ccsr_ddr __iomem *ddr = in sdram_init() local
23 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); in sdram_init()
24 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); in sdram_init()
25 __raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg); in sdram_init()
26 __raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2); in sdram_init()
27 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); in sdram_init()
29 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); in sdram_init()
30 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); in sdram_init()
31 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); in sdram_init()
32 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); in sdram_init()
[all …]
/OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dspd_sdram.c27 volatile ddr83xx_t *ddr = &immap->ddr; in board_add_ram_info() local
30 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) in board_add_ram_info()
34 if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16) in board_add_ram_info()
36 else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32) in board_add_ram_info()
41 if (ddr->sdram_cfg & SDRAM_CFG_32_BE) in board_add_ram_info()
47 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) in board_add_ram_info()
126 volatile ddr83xx_t *ddr = &immap->ddr; in spd_sdram() local
157 clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0); in spd_sdram()
169 debug("DDR: Module mem type is %02X\n", spd.mem_type); in spd_sdram()
181 printf("DDR: The number of physical bank is %02X\n", n_ranks); in spd_sdram()
[all …]
H A Decc.c19 struct ccsr_ddr __iomem *ddr = &immap->ddr; in ecc_print_status() local
21 ddr83xx_t *ddr = &immap->ddr; in ecc_print_status() local
25 (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); in ecc_print_status()
30 (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0); in ecc_print_status()
32 (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0); in ecc_print_status()
34 (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0); in ecc_print_status()
39 (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0); in ecc_print_status()
41 (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0); in ecc_print_status()
43 (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0); in ecc_print_status()
47 ddr->data_err_inject_hi, ddr->data_err_inject_lo); in ecc_print_status()
[all …]
/OK3568_Linux_fs/u-boot/board/sbc8641d/
H A Dsbc8641d.c52 debug (" DDR: "); in dram_init()
100 volatile struct ccsr_ddr *ddr = &immap->im_ddr1; in fixed_sdram() local
102 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; in fixed_sdram()
103 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS; in fixed_sdram()
104 ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS; in fixed_sdram()
105 ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS; in fixed_sdram()
106 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
107 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG; in fixed_sdram()
108 ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG; in fixed_sdram()
109 ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG; in fixed_sdram()
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp_mc_static.h12 {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
14 {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
17 {0x00001408, 0x43149775}, /*DDR SDRAM Timing (Low) Register */
18 /* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
19 {0x0000140C, 0x38d83fe0}, /*DDR SDRAM Timing (High) Register */
22 {0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */
24 {0x00001410, 0x040F0000}, /*DDR SDRAM Open Pages Control Register */
27 {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
28 {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
29 {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */
[all …]
/OK3568_Linux_fs/u-boot/post/cpu/mpc83xx/
H A Decc.c24 static inline void ecc_clear(ddr83xx_t *ddr) in ecc_clear() argument
27 __raw_writel(0, &ddr->capture_address); in ecc_clear()
28 __raw_writel(0, &ddr->capture_data_hi); in ecc_clear()
29 __raw_writel(0, &ddr->capture_data_lo); in ecc_clear()
30 __raw_writel(0, &ddr->capture_ecc); in ecc_clear()
31 __raw_writel(0, &ddr->capture_attributes); in ecc_clear()
34 out_be32(&ddr->err_sbe, 1 << ECC_ERROR_MAN_SBET_SHIFT); in ecc_clear()
37 out_be32(&ddr->err_detect, ECC_ERROR_DETECT_MME |\ in ecc_clear()
51 ddr83xx_t *ddr = &((immap_t *)CONFIG_SYS_IMMR)->ddr; in ecc_post_test() local
63 if (__raw_readl(&ddr->err_disable) & ECC_ERROR_ENABLE) { in ecc_post_test()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/bcm/
H A Dbrcm,brcmstb.txt148 independently (control registers, DDR PHYs, etc.). One might consider
163 == DDR PHY control
165 Control registers for this memory controller's DDR PHY.
169 "brcm,brcmstb-ddr-phy-v71.1"
170 "brcm,brcmstb-ddr-phy-v72.0"
171 "brcm,brcmstb-ddr-phy-v225.1"
172 "brcm,brcmstb-ddr-phy-v240.1"
173 "brcm,brcmstb-ddr-phy-v240.2"
175 - reg : the DDR PHY register range
177 == DDR SHIMPHY
[all …]
/OK3568_Linux_fs/u-boot/board/sbc8548/
H A Dddr.c60 * existed on earlier boards; the workaround moved the DDR
80 printf("DDR: failed to read SPD from addr %u\n", i2c_address); in get_spd()
92 struct ccsr_ddr __iomem *ddr = in fixed_sdram() local
95 out_be32(&ddr->cs0_bnds, 0x0000007f); in fixed_sdram()
96 out_be32(&ddr->cs1_bnds, 0x008000ff); in fixed_sdram()
97 out_be32(&ddr->cs2_bnds, 0x00000000); in fixed_sdram()
98 out_be32(&ddr->cs3_bnds, 0x00000000); in fixed_sdram()
100 out_be32(&ddr->cs0_config, 0x80010101); in fixed_sdram()
101 out_be32(&ddr->cs1_config, 0x80010101); in fixed_sdram()
102 out_be32(&ddr->cs2_config, 0x00000000); in fixed_sdram()
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/bsc9131rdb/
H A Dspl_minimal.c23 struct ccsr_ddr __iomem *ddr = in sdram_init() local
26 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); in sdram_init()
27 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); in sdram_init()
29 __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); in sdram_init()
30 __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); in sdram_init()
32 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); in sdram_init()
33 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); in sdram_init()
34 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); in sdram_init()
35 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); in sdram_init()
37 __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); in sdram_init()
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/ls1021aiot/
H A Dls1021aiot.c50 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; in ddrmc_init() local
53 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); in ddrmc_init()
55 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); in ddrmc_init()
56 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); in ddrmc_init()
58 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); in ddrmc_init()
59 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); in ddrmc_init()
60 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); in ddrmc_init()
61 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); in ddrmc_init()
62 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); in ddrmc_init()
63 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); in ddrmc_init()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mips/brcm/
H A Dsoc.txt45 independently (control registers, DDR PHYs, etc.). One might consider
58 the entire memory controller (including all sub nodes: DDR PHY,
75 memc-ddr@2000 {
79 ddr-phy@6000 {
86 == DDR PHY control
88 Control registers for this memory controller's DDR PHY.
92 "brcm,brcmstb-ddr-phy-v64.5"
93 "brcm,brcmstb-ddr-phy"
95 - reg : the DDR PHY register range and length
99 ddr-phy@6000 {
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/mpc8349emds/
H A Dmpc8349emds.c59 /* DDR SDRAM - Main SODIMM */ in dram_init()
78 /* set total bus SDRAM size(bytes) -- DDR */ in dram_init()
92 u32 ddr_size = msize << 20; /* DDR size in bytes */ in fixed_sdram()
99 #warning Currenly any ddr size other than 256 is not supported in fixed_sdram()
102 im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS; in fixed_sdram()
103 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; in fixed_sdram()
104 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
105 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
106 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
107 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; in fixed_sdram()
[all …]
/OK3568_Linux_fs/u-boot/cmd/ddr_tool/
H A DKconfig1 menu "DDR Tool"
4 bool "Enable DDR Tool"
6 This enable ddr tool such as ddr dq eye, ddr test tool, memtester and stressapptest.
9 bool "Enable DDR DQ eye fuction"
12 This enable ddr dq eye fuction.
15 bool "Enable ddr test tool"
18 This enable ddr test tool code.
21 bool "Enable memtester for ddr"
24 This enables memtester for ddr.
27 bool "Enable stressapptest for ddr"
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/mpc8308rdb/
H A Dsdram.c41 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
42 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
45 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
47 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
48 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
49 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
50 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
51 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
53 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
54 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
[all …]
/OK3568_Linux_fs/u-boot/board/mpc8308_p1m/
H A Dsdram.c37 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
38 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
41 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
43 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
44 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
45 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
46 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
47 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
49 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
50 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/mpc8315erdb/
H A Dsdram.c58 im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; in fixed_sdram()
59 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
62 im->ddr.cs_config[1] = 0; in fixed_sdram()
64 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; in fixed_sdram()
65 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; in fixed_sdram()
66 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
67 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
68 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
71 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI; in fixed_sdram()
73 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; in fixed_sdram()
[all …]
/OK3568_Linux_fs/u-boot/board/gdsys/mpc8308/
H A Dsdram.c42 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
43 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
46 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
48 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
49 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
50 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
51 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
52 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
54 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
55 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
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