1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2008-2011 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/io.h>
9*4882a593Smuzhiyun #include <asm/processor.h>
10*4882a593Smuzhiyun #include <fsl_ddr_sdram.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
13*4882a593Smuzhiyun #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
14*4882a593Smuzhiyun #endif
15*4882a593Smuzhiyun
fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t * regs,unsigned int ctrl_num,int step)16*4882a593Smuzhiyun void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
17*4882a593Smuzhiyun unsigned int ctrl_num, int step)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun unsigned int i;
20*4882a593Smuzhiyun struct ccsr_ddr __iomem *ddr =
21*4882a593Smuzhiyun (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
24*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
25*4882a593Smuzhiyun uint svr;
26*4882a593Smuzhiyun #endif
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun if (ctrl_num) {
29*4882a593Smuzhiyun printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
30*4882a593Smuzhiyun return;
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
34*4882a593Smuzhiyun /*
35*4882a593Smuzhiyun * Set the DDR IO receiver to an acceptable bias point.
36*4882a593Smuzhiyun * Fixed in Rev 2.1.
37*4882a593Smuzhiyun */
38*4882a593Smuzhiyun svr = get_svr();
39*4882a593Smuzhiyun if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) {
40*4882a593Smuzhiyun if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) ==
41*4882a593Smuzhiyun SDRAM_CFG_SDRAM_TYPE_DDR2)
42*4882a593Smuzhiyun out_be32(&gur->ddrioovcr, 0x90000000);
43*4882a593Smuzhiyun else
44*4882a593Smuzhiyun out_be32(&gur->ddrioovcr, 0xA8000000);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun #endif
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
49*4882a593Smuzhiyun if (i == 0) {
50*4882a593Smuzhiyun out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
51*4882a593Smuzhiyun out_be32(&ddr->cs0_config, regs->cs[i].config);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun } else if (i == 1) {
54*4882a593Smuzhiyun out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
55*4882a593Smuzhiyun out_be32(&ddr->cs1_config, regs->cs[i].config);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun } else if (i == 2) {
58*4882a593Smuzhiyun out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
59*4882a593Smuzhiyun out_be32(&ddr->cs2_config, regs->cs[i].config);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun } else if (i == 3) {
62*4882a593Smuzhiyun out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
63*4882a593Smuzhiyun out_be32(&ddr->cs3_config, regs->cs[i].config);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
68*4882a593Smuzhiyun out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
69*4882a593Smuzhiyun out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
70*4882a593Smuzhiyun out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
71*4882a593Smuzhiyun out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
72*4882a593Smuzhiyun out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
73*4882a593Smuzhiyun out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
74*4882a593Smuzhiyun out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
75*4882a593Smuzhiyun out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
76*4882a593Smuzhiyun out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
77*4882a593Smuzhiyun out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
78*4882a593Smuzhiyun out_be32(&ddr->init_addr, regs->ddr_init_addr);
79*4882a593Smuzhiyun out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /*
82*4882a593Smuzhiyun * 200 painful micro-seconds must elapse between
83*4882a593Smuzhiyun * the DDR clock setup and the DDR config enable.
84*4882a593Smuzhiyun */
85*4882a593Smuzhiyun udelay(200);
86*4882a593Smuzhiyun asm volatile("sync;isync");
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
91*4882a593Smuzhiyun while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
92*4882a593Smuzhiyun udelay(10000); /* throttle polling rate */
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun }
95