1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2010
3*4882a593Smuzhiyun * Eastman Kodak Company, <www.kodak.com>
4*4882a593Smuzhiyun * Michael Zaidman, <michael.zaidman@kodak.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * The code is based on the cpu/mpc83xx/ecc.c written by
7*4882a593Smuzhiyun * Dave Liu <daveliu@freescale.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <mpc83xx.h>
14*4882a593Smuzhiyun #include <watchdog.h>
15*4882a593Smuzhiyun #include <asm/io.h>
16*4882a593Smuzhiyun #include <post.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #if CONFIG_POST & CONFIG_SYS_POST_ECC
19*4882a593Smuzhiyun /*
20*4882a593Smuzhiyun * We use the RAW I/O accessors where possible in order to
21*4882a593Smuzhiyun * achieve performance goal, since the test's execution time
22*4882a593Smuzhiyun * affects the board start up time.
23*4882a593Smuzhiyun */
ecc_clear(ddr83xx_t * ddr)24*4882a593Smuzhiyun static inline void ecc_clear(ddr83xx_t *ddr)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun /* Clear capture registers */
27*4882a593Smuzhiyun __raw_writel(0, &ddr->capture_address);
28*4882a593Smuzhiyun __raw_writel(0, &ddr->capture_data_hi);
29*4882a593Smuzhiyun __raw_writel(0, &ddr->capture_data_lo);
30*4882a593Smuzhiyun __raw_writel(0, &ddr->capture_ecc);
31*4882a593Smuzhiyun __raw_writel(0, &ddr->capture_attributes);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* Clear SBEC and set SBET to 1 */
34*4882a593Smuzhiyun out_be32(&ddr->err_sbe, 1 << ECC_ERROR_MAN_SBET_SHIFT);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* Clear Error Detect register */
37*4882a593Smuzhiyun out_be32(&ddr->err_detect, ECC_ERROR_DETECT_MME |\
38*4882a593Smuzhiyun ECC_ERROR_DETECT_MBE |\
39*4882a593Smuzhiyun ECC_ERROR_DETECT_SBE |\
40*4882a593Smuzhiyun ECC_ERROR_DETECT_MSE);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun isync();
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
ecc_post_test(int flags)45*4882a593Smuzhiyun int ecc_post_test(int flags)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun int ret = 0;
48*4882a593Smuzhiyun int int_state;
49*4882a593Smuzhiyun int errbit;
50*4882a593Smuzhiyun u32 pattern[2], writeback[2], retval[2];
51*4882a593Smuzhiyun ddr83xx_t *ddr = &((immap_t *)CONFIG_SYS_IMMR)->ddr;
52*4882a593Smuzhiyun volatile u64 *addr = (u64 *)CONFIG_SYS_POST_ECC_START_ADDR;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* The pattern is written into memory to generate error */
55*4882a593Smuzhiyun pattern[0] = 0xfedcba98UL;
56*4882a593Smuzhiyun pattern[1] = 0x76543210UL;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* After injecting error, re-initialize the memory with the value */
59*4882a593Smuzhiyun writeback[0] = ~pattern[0];
60*4882a593Smuzhiyun writeback[1] = ~pattern[1];
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* Check if ECC is enabled */
63*4882a593Smuzhiyun if (__raw_readl(&ddr->err_disable) & ECC_ERROR_ENABLE) {
64*4882a593Smuzhiyun debug("DDR's ECC is not enabled, skipping the ECC POST.\n");
65*4882a593Smuzhiyun return 0;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun int_state = disable_interrupts();
69*4882a593Smuzhiyun icache_enable();
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #ifdef CONFIG_DDR_32BIT
72*4882a593Smuzhiyun /* It seems like no one really uses the CONFIG_DDR_32BIT mode */
73*4882a593Smuzhiyun #error "Add ECC POST support for CONFIG_DDR_32BIT here!"
74*4882a593Smuzhiyun #else
75*4882a593Smuzhiyun for (addr = (u64*)CONFIG_SYS_POST_ECC_START_ADDR, errbit=0;
76*4882a593Smuzhiyun addr < (u64*)CONFIG_SYS_POST_ECC_STOP_ADDR; addr++, errbit++ ) {
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun WATCHDOG_RESET();
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun ecc_clear(ddr);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Enable error injection */
83*4882a593Smuzhiyun setbits_be32(&ddr->ecc_err_inject, ECC_ERR_INJECT_EIEN);
84*4882a593Smuzhiyun sync();
85*4882a593Smuzhiyun isync();
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* Set bit to be injected */
88*4882a593Smuzhiyun if (errbit < 32) {
89*4882a593Smuzhiyun __raw_writel(1 << errbit, &ddr->data_err_inject_lo);
90*4882a593Smuzhiyun __raw_writel(0, &ddr->data_err_inject_hi);
91*4882a593Smuzhiyun } else {
92*4882a593Smuzhiyun __raw_writel(0, &ddr->data_err_inject_lo);
93*4882a593Smuzhiyun __raw_writel(1<<(errbit-32), &ddr->data_err_inject_hi);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun sync();
96*4882a593Smuzhiyun isync();
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun /* Write memory location injecting SBE */
99*4882a593Smuzhiyun ppcDWstore((u32*)addr, pattern);
100*4882a593Smuzhiyun sync();
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* Disable error injection */
103*4882a593Smuzhiyun clrbits_be32(&ddr->ecc_err_inject, ECC_ERR_INJECT_EIEN);
104*4882a593Smuzhiyun sync();
105*4882a593Smuzhiyun isync();
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* Data read should generate SBE */
108*4882a593Smuzhiyun ppcDWload((u32*)addr, retval);
109*4882a593Smuzhiyun sync();
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun if (!(__raw_readl(&ddr->err_detect) & ECC_ERROR_DETECT_SBE) ||
112*4882a593Smuzhiyun (__raw_readl(&ddr->data_err_inject_hi) !=
113*4882a593Smuzhiyun (__raw_readl(&ddr->capture_data_hi) ^ pattern[0])) ||
114*4882a593Smuzhiyun (__raw_readl(&ddr->data_err_inject_lo) !=
115*4882a593Smuzhiyun (__raw_readl(&ddr->capture_data_lo) ^ pattern[1]))) {
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun post_log("ECC failed to detect SBE error at %08x, "
118*4882a593Smuzhiyun "SBE injection mask %08x-%08x, wrote "
119*4882a593Smuzhiyun "%08x-%08x, read %08x-%08x\n", addr,
120*4882a593Smuzhiyun ddr->data_err_inject_hi,
121*4882a593Smuzhiyun ddr->data_err_inject_lo,
122*4882a593Smuzhiyun pattern[0], pattern[1],
123*4882a593Smuzhiyun retval[0], retval[1]);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun printf("ERR_DETECT Reg: %08x\n", ddr->err_detect);
126*4882a593Smuzhiyun printf("ECC CAPTURE_DATA Reg: %08x-%08x\n",
127*4882a593Smuzhiyun ddr->capture_data_hi, ddr->capture_data_lo);
128*4882a593Smuzhiyun ret = 1;
129*4882a593Smuzhiyun break;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun /* Re-initialize the ECC memory */
133*4882a593Smuzhiyun ppcDWstore((u32*)addr, writeback);
134*4882a593Smuzhiyun sync();
135*4882a593Smuzhiyun isync();
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun errbit %= 63;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun #endif /* !CONFIG_DDR_32BIT */
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun ecc_clear(ddr);
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun icache_disable();
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun if (int_state)
146*4882a593Smuzhiyun enable_interrupts();
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun return ret;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun #endif
151