1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2007 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Authors: Nick.Spence@freescale.com
6*4882a593Smuzhiyun * Wilson.Lo@freescale.com
7*4882a593Smuzhiyun * scottwood@freescale.com
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This files is mostly identical to the original from
10*4882a593Smuzhiyun * board\freescale\mpc8315erdb\sdram.c
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <common.h>
16*4882a593Smuzhiyun #include <mpc83xx.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <asm/bitops.h>
19*4882a593Smuzhiyun #include <asm/io.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <asm/processor.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Fixed sdram init -- doesn't use serial presence detect.
26*4882a593Smuzhiyun *
27*4882a593Smuzhiyun * This is useful for faster booting in configs where the RAM is unlikely
28*4882a593Smuzhiyun * to be changed, or for things like NAND booting where space is tight.
29*4882a593Smuzhiyun */
fixed_sdram(void)30*4882a593Smuzhiyun static long fixed_sdram(void)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
33*4882a593Smuzhiyun u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
34*4882a593Smuzhiyun u32 msize_log2 = __ilog2(msize);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun out_be32(&im->sysconf.ddrlaw[0].bar,
37*4882a593Smuzhiyun CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
38*4882a593Smuzhiyun out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
39*4882a593Smuzhiyun out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
42*4882a593Smuzhiyun out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* Currently we use only one CS, so disable the other bank. */
45*4882a593Smuzhiyun out_be32(&im->ddr.cs_config[1], 0);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
48*4882a593Smuzhiyun out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
49*4882a593Smuzhiyun out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
50*4882a593Smuzhiyun out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
51*4882a593Smuzhiyun out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
54*4882a593Smuzhiyun out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
55*4882a593Smuzhiyun out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
56*4882a593Smuzhiyun out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
59*4882a593Smuzhiyun sync();
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* enable DDR controller */
62*4882a593Smuzhiyun setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
63*4882a593Smuzhiyun sync();
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
dram_init(void)68*4882a593Smuzhiyun int dram_init(void)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
71*4882a593Smuzhiyun u32 msize;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
74*4882a593Smuzhiyun return -ENXIO;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /* DDR SDRAM */
77*4882a593Smuzhiyun msize = fixed_sdram();
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* return total bus SDRAM size(bytes) -- DDR */
80*4882a593Smuzhiyun gd->ram_size = msize;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun return 0;
83*4882a593Smuzhiyun }
84