1*4882a593Smuzhiyun* Broadcom cable/DSL/settop platforms 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843" 6*4882a593Smuzhiyun "brcm,bcm3384-viper", "brcm,bcm33843-viper" 7*4882a593Smuzhiyun "brcm,bcm6328", "brcm,bcm6358", "brcm,bcm6362", "brcm,bcm6368", 8*4882a593Smuzhiyun "brcm,bcm63168", "brcm,bcm63268", 9*4882a593Smuzhiyun "brcm,bcm7125", "brcm,bcm7346", "brcm,bcm7358", "brcm,bcm7360", 10*4882a593Smuzhiyun "brcm,bcm7362", "brcm,bcm7420", "brcm,bcm7425" 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunThe experimental -viper variants are for running Linux on the 3384's 13*4882a593SmuzhiyunBMIPS4355 cable modem CPU instead of the BMIPS5000 application processor. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunPower management 16*4882a593Smuzhiyun---------------- 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunFor power management (particularly, S2/S3/S5 system suspend), the following SoC 19*4882a593Smuzhiyuncomponents are needed: 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun= Always-On control block (AON CTRL) 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunThis hardware provides control registers for the "always-on" (even in low-power 24*4882a593Smuzhiyunmodes) hardware, such as the Power Management State Machine (PMSM). 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunRequired properties: 27*4882a593Smuzhiyun- compatible : should be one of 28*4882a593Smuzhiyun "brcm,bcm7425-aon-ctrl" 29*4882a593Smuzhiyun "brcm,bcm7429-aon-ctrl" 30*4882a593Smuzhiyun "brcm,bcm7435-aon-ctrl" and 31*4882a593Smuzhiyun "brcm,brcmstb-aon-ctrl" 32*4882a593Smuzhiyun- reg : the register start and length for the AON CTRL block 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunExample: 35*4882a593Smuzhiyun 36*4882a593Smuzhiyunsyscon@410000 { 37*4882a593Smuzhiyun compatible = "brcm,bcm7425-aon-ctrl", "brcm,brcmstb-aon-ctrl"; 38*4882a593Smuzhiyun reg = <0x410000 0x400>; 39*4882a593Smuzhiyun}; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun= Memory controllers 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunA Broadcom STB SoC typically has a number of independent memory controllers, 44*4882a593Smuzhiyuneach of which may have several associated hardware blocks, which are versioned 45*4882a593Smuzhiyunindependently (control registers, DDR PHYs, etc.). One might consider 46*4882a593Smuzhiyundescribing these controllers as a parent "memory controllers" block, which 47*4882a593Smuzhiyuncontains N sub-nodes (one for each controller in the system), each of which is 48*4882a593Smuzhiyunassociated with a number of hardware register resources (e.g., its PHY. 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun== MEMC (MEMory Controller) 51*4882a593Smuzhiyun 52*4882a593SmuzhiyunRepresents a single memory controller instance. 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunRequired properties: 55*4882a593Smuzhiyun- compatible : should contain "brcm,brcmstb-memc" and "simple-bus" 56*4882a593Smuzhiyun- ranges : should contain the child address in the parent address 57*4882a593Smuzhiyun space, must be 0 here, and the register start and length of 58*4882a593Smuzhiyun the entire memory controller (including all sub nodes: DDR PHY, 59*4882a593Smuzhiyun arbiter, etc.) 60*4882a593Smuzhiyun- #address-cells : must be 1 61*4882a593Smuzhiyun- #size-cells : must be 1 62*4882a593Smuzhiyun 63*4882a593SmuzhiyunExample: 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun memory-controller@0 { 66*4882a593Smuzhiyun compatible = "brcm,brcmstb-memc", "simple-bus"; 67*4882a593Smuzhiyun ranges = <0x0 0x0 0xa000>; 68*4882a593Smuzhiyun #address-cells = <1>; 69*4882a593Smuzhiyun #size-cells = <1>; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun memc-arb@1000 { 72*4882a593Smuzhiyun ... 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun memc-ddr@2000 { 76*4882a593Smuzhiyun ... 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun ddr-phy@6000 { 80*4882a593Smuzhiyun ... 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593SmuzhiyunShould contain subnodes for any of the following relevant hardware resources: 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun== DDR PHY control 87*4882a593Smuzhiyun 88*4882a593SmuzhiyunControl registers for this memory controller's DDR PHY. 89*4882a593Smuzhiyun 90*4882a593SmuzhiyunRequired properties: 91*4882a593Smuzhiyun- compatible : should contain one of these 92*4882a593Smuzhiyun "brcm,brcmstb-ddr-phy-v64.5" 93*4882a593Smuzhiyun "brcm,brcmstb-ddr-phy" 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun- reg : the DDR PHY register range and length 96*4882a593Smuzhiyun 97*4882a593SmuzhiyunExample: 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun ddr-phy@6000 { 100*4882a593Smuzhiyun compatible = "brcm,brcmstb-ddr-phy-v64.5"; 101*4882a593Smuzhiyun reg = <0x6000 0xc8>; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun== DDR memory controller sequencer 105*4882a593Smuzhiyun 106*4882a593SmuzhiyunControl registers for this memory controller's DDR memory sequencer 107*4882a593Smuzhiyun 108*4882a593SmuzhiyunRequired properties: 109*4882a593Smuzhiyun- compatible : should contain one of these 110*4882a593Smuzhiyun "brcm,bcm7425-memc-ddr" 111*4882a593Smuzhiyun "brcm,bcm7429-memc-ddr" 112*4882a593Smuzhiyun "brcm,bcm7435-memc-ddr" and 113*4882a593Smuzhiyun "brcm,brcmstb-memc-ddr" 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun- reg : the DDR sequencer register range and length 116*4882a593Smuzhiyun 117*4882a593SmuzhiyunExample: 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun memc-ddr@2000 { 120*4882a593Smuzhiyun compatible = "brcm,bcm7425-memc-ddr", "brcm,brcmstb-memc-ddr"; 121*4882a593Smuzhiyun reg = <0x2000 0x300>; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun== MEMC Arbiter 125*4882a593Smuzhiyun 126*4882a593SmuzhiyunThe memory controller arbiter is responsible for memory clients allocation 127*4882a593Smuzhiyun(bandwidth, priorities etc.) and needs to have its contents restored during 128*4882a593Smuzhiyundeep sleep states (S3). 129*4882a593Smuzhiyun 130*4882a593SmuzhiyunRequired properties: 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun- compatible : should contain one of these 133*4882a593Smuzhiyun "brcm,brcmstb-memc-arb-v10.0.0.0" 134*4882a593Smuzhiyun "brcm,brcmstb-memc-arb" 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun- reg : the DDR Arbiter register range and length 137*4882a593Smuzhiyun 138*4882a593SmuzhiyunExample: 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun memc-arb@1000 { 141*4882a593Smuzhiyun compatible = "brcm,brcmstb-memc-arb-v10.0.0.0"; 142*4882a593Smuzhiyun reg = <0x1000 0x248>; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun== Timers 146*4882a593Smuzhiyun 147*4882a593SmuzhiyunThe Broadcom STB chips contain a timer block with several general purpose 148*4882a593Smuzhiyuntimers that can be used. 149*4882a593Smuzhiyun 150*4882a593SmuzhiyunRequired properties: 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun- compatible : should contain one of: 153*4882a593Smuzhiyun "brcm,bcm7425-timers" 154*4882a593Smuzhiyun "brcm,bcm7429-timers" 155*4882a593Smuzhiyun "brcm,bcm7435-timers" and 156*4882a593Smuzhiyun "brcm,brcmstb-timers" 157*4882a593Smuzhiyun- reg : the timers register range 158*4882a593Smuzhiyun- interrupts : the interrupt line for this timer block 159*4882a593Smuzhiyun 160*4882a593SmuzhiyunExample: 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun timers: timer@4067c0 { 163*4882a593Smuzhiyun compatible = "brcm,bcm7425-timers", "brcm,brcmstb-timers"; 164*4882a593Smuzhiyun reg = <0x4067c0 0x40>; 165*4882a593Smuzhiyun interrupts = <&periph_intc 19>; 166*4882a593Smuzhiyun }; 167