1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Dave Liu <daveliu@freescale.com>
5*4882a593Smuzhiyun * based on the contribution of Marian Balakowicz <m8@semihalf.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <mpc83xx.h>
12*4882a593Smuzhiyun #include <command.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
ecc_print_status(void)15*4882a593Smuzhiyun void ecc_print_status(void)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
18*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_DDR2
19*4882a593Smuzhiyun struct ccsr_ddr __iomem *ddr = &immap->ddr;
20*4882a593Smuzhiyun #else
21*4882a593Smuzhiyun ddr83xx_t *ddr = &immap->ddr;
22*4882a593Smuzhiyun #endif
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun printf("\nECC mode: %s\n\n",
25*4882a593Smuzhiyun (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Interrupts */
28*4882a593Smuzhiyun printf("Memory Error Interrupt Enable:\n");
29*4882a593Smuzhiyun printf(" Multiple-Bit Error Interrupt Enable: %d\n",
30*4882a593Smuzhiyun (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
31*4882a593Smuzhiyun printf(" Single-Bit Error Interrupt Enable: %d\n",
32*4882a593Smuzhiyun (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
33*4882a593Smuzhiyun printf(" Memory Select Error Interrupt Enable: %d\n\n",
34*4882a593Smuzhiyun (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* Error disable */
37*4882a593Smuzhiyun printf("Memory Error Disable:\n");
38*4882a593Smuzhiyun printf(" Multiple-Bit Error Disable: %d\n",
39*4882a593Smuzhiyun (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
40*4882a593Smuzhiyun printf(" Single-Bit Error Disable: %d\n",
41*4882a593Smuzhiyun (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
42*4882a593Smuzhiyun printf(" Memory Select Error Disable: %d\n\n",
43*4882a593Smuzhiyun (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* Error injection */
46*4882a593Smuzhiyun printf("Memory Data Path Error Injection Mask High/Low: %08x %08x\n",
47*4882a593Smuzhiyun ddr->data_err_inject_hi, ddr->data_err_inject_lo);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun printf("Memory Data Path Error Injection Mask ECC:\n");
50*4882a593Smuzhiyun printf(" ECC Mirror Byte: %d\n",
51*4882a593Smuzhiyun (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
52*4882a593Smuzhiyun printf(" ECC Injection Enable: %d\n",
53*4882a593Smuzhiyun (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
54*4882a593Smuzhiyun printf(" ECC Error Injection Mask: 0x%02x\n\n",
55*4882a593Smuzhiyun ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* SBE counter/threshold */
58*4882a593Smuzhiyun printf("Memory Single-Bit Error Management (0..255):\n");
59*4882a593Smuzhiyun printf(" Single-Bit Error Threshold: %d\n",
60*4882a593Smuzhiyun (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
61*4882a593Smuzhiyun printf(" Single-Bit Error Counter: %d\n\n",
62*4882a593Smuzhiyun (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* Error detect */
65*4882a593Smuzhiyun printf("Memory Error Detect:\n");
66*4882a593Smuzhiyun printf(" Multiple Memory Errors: %d\n",
67*4882a593Smuzhiyun (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
68*4882a593Smuzhiyun printf(" Multiple-Bit Error: %d\n",
69*4882a593Smuzhiyun (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
70*4882a593Smuzhiyun printf(" Single-Bit Error: %d\n",
71*4882a593Smuzhiyun (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
72*4882a593Smuzhiyun printf(" Memory Select Error: %d\n\n",
73*4882a593Smuzhiyun (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Capture data */
76*4882a593Smuzhiyun printf("Memory Error Address Capture: 0x%08x\n", ddr->capture_address);
77*4882a593Smuzhiyun printf("Memory Data Path Read Capture High/Low: %08x %08x\n",
78*4882a593Smuzhiyun ddr->capture_data_hi, ddr->capture_data_lo);
79*4882a593Smuzhiyun printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
80*4882a593Smuzhiyun ddr->capture_ecc & CAPTURE_ECC_ECE);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun printf("Memory Error Attributes Capture:\n");
83*4882a593Smuzhiyun printf(" Data Beat Number: %d\n",
84*4882a593Smuzhiyun (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >>
85*4882a593Smuzhiyun ECC_CAPT_ATTR_BNUM_SHIFT);
86*4882a593Smuzhiyun printf(" Transaction Size: %d\n",
87*4882a593Smuzhiyun (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >>
88*4882a593Smuzhiyun ECC_CAPT_ATTR_TSIZ_SHIFT);
89*4882a593Smuzhiyun printf(" Transaction Source: %d\n",
90*4882a593Smuzhiyun (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >>
91*4882a593Smuzhiyun ECC_CAPT_ATTR_TSRC_SHIFT);
92*4882a593Smuzhiyun printf(" Transaction Type: %d\n",
93*4882a593Smuzhiyun (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >>
94*4882a593Smuzhiyun ECC_CAPT_ATTR_TTYP_SHIFT);
95*4882a593Smuzhiyun printf(" Error Information Valid: %d\n\n",
96*4882a593Smuzhiyun ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
do_ecc(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])99*4882a593Smuzhiyun int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
102*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_DDR2
103*4882a593Smuzhiyun struct ccsr_ddr __iomem *ddr = &immap->ddr;
104*4882a593Smuzhiyun #else
105*4882a593Smuzhiyun ddr83xx_t *ddr = &immap->ddr;
106*4882a593Smuzhiyun #endif
107*4882a593Smuzhiyun volatile u32 val;
108*4882a593Smuzhiyun u64 *addr;
109*4882a593Smuzhiyun u32 count;
110*4882a593Smuzhiyun register u64 *i;
111*4882a593Smuzhiyun u32 ret[2];
112*4882a593Smuzhiyun u32 pattern[2];
113*4882a593Smuzhiyun u32 writeback[2];
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /* The pattern is written into memory to generate error */
116*4882a593Smuzhiyun pattern[0] = 0xfedcba98UL;
117*4882a593Smuzhiyun pattern[1] = 0x76543210UL;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /* After injecting error, re-initialize the memory with the value */
120*4882a593Smuzhiyun writeback[0] = 0x01234567UL;
121*4882a593Smuzhiyun writeback[1] = 0x89abcdefUL;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun if (argc > 4)
124*4882a593Smuzhiyun return cmd_usage(cmdtp);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun if (argc == 2) {
127*4882a593Smuzhiyun if (strcmp(argv[1], "status") == 0) {
128*4882a593Smuzhiyun ecc_print_status();
129*4882a593Smuzhiyun return 0;
130*4882a593Smuzhiyun } else if (strcmp(argv[1], "captureclear") == 0) {
131*4882a593Smuzhiyun ddr->capture_address = 0;
132*4882a593Smuzhiyun ddr->capture_data_hi = 0;
133*4882a593Smuzhiyun ddr->capture_data_lo = 0;
134*4882a593Smuzhiyun ddr->capture_ecc = 0;
135*4882a593Smuzhiyun ddr->capture_attributes = 0;
136*4882a593Smuzhiyun return 0;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun if (argc == 3) {
140*4882a593Smuzhiyun if (strcmp(argv[1], "sbecnt") == 0) {
141*4882a593Smuzhiyun val = simple_strtoul(argv[2], NULL, 10);
142*4882a593Smuzhiyun if (val > 255) {
143*4882a593Smuzhiyun printf("Incorrect Counter value, "
144*4882a593Smuzhiyun "should be 0..255\n");
145*4882a593Smuzhiyun return 1;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
149*4882a593Smuzhiyun val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun ddr->err_sbe = val;
152*4882a593Smuzhiyun return 0;
153*4882a593Smuzhiyun } else if (strcmp(argv[1], "sbethr") == 0) {
154*4882a593Smuzhiyun val = simple_strtoul(argv[2], NULL, 10);
155*4882a593Smuzhiyun if (val > 255) {
156*4882a593Smuzhiyun printf("Incorrect Counter value, "
157*4882a593Smuzhiyun "should be 0..255\n");
158*4882a593Smuzhiyun return 1;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun val = (val << ECC_ERROR_MAN_SBET_SHIFT);
162*4882a593Smuzhiyun val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun ddr->err_sbe = val;
165*4882a593Smuzhiyun return 0;
166*4882a593Smuzhiyun } else if (strcmp(argv[1], "errdisable") == 0) {
167*4882a593Smuzhiyun val = ddr->err_disable;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun if (strcmp(argv[2], "+sbe") == 0) {
170*4882a593Smuzhiyun val |= ECC_ERROR_DISABLE_SBED;
171*4882a593Smuzhiyun } else if (strcmp(argv[2], "+mbe") == 0) {
172*4882a593Smuzhiyun val |= ECC_ERROR_DISABLE_MBED;
173*4882a593Smuzhiyun } else if (strcmp(argv[2], "+mse") == 0) {
174*4882a593Smuzhiyun val |= ECC_ERROR_DISABLE_MSED;
175*4882a593Smuzhiyun } else if (strcmp(argv[2], "+all") == 0) {
176*4882a593Smuzhiyun val |= (ECC_ERROR_DISABLE_SBED |
177*4882a593Smuzhiyun ECC_ERROR_DISABLE_MBED |
178*4882a593Smuzhiyun ECC_ERROR_DISABLE_MSED);
179*4882a593Smuzhiyun } else if (strcmp(argv[2], "-sbe") == 0) {
180*4882a593Smuzhiyun val &= ~ECC_ERROR_DISABLE_SBED;
181*4882a593Smuzhiyun } else if (strcmp(argv[2], "-mbe") == 0) {
182*4882a593Smuzhiyun val &= ~ECC_ERROR_DISABLE_MBED;
183*4882a593Smuzhiyun } else if (strcmp(argv[2], "-mse") == 0) {
184*4882a593Smuzhiyun val &= ~ECC_ERROR_DISABLE_MSED;
185*4882a593Smuzhiyun } else if (strcmp(argv[2], "-all") == 0) {
186*4882a593Smuzhiyun val &= ~(ECC_ERROR_DISABLE_SBED |
187*4882a593Smuzhiyun ECC_ERROR_DISABLE_MBED |
188*4882a593Smuzhiyun ECC_ERROR_DISABLE_MSED);
189*4882a593Smuzhiyun } else {
190*4882a593Smuzhiyun printf("Incorrect err_disable field\n");
191*4882a593Smuzhiyun return 1;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun ddr->err_disable = val;
195*4882a593Smuzhiyun __asm__ __volatile__("sync");
196*4882a593Smuzhiyun __asm__ __volatile__("isync");
197*4882a593Smuzhiyun return 0;
198*4882a593Smuzhiyun } else if (strcmp(argv[1], "errdetectclr") == 0) {
199*4882a593Smuzhiyun val = ddr->err_detect;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun if (strcmp(argv[2], "mme") == 0) {
202*4882a593Smuzhiyun val |= ECC_ERROR_DETECT_MME;
203*4882a593Smuzhiyun } else if (strcmp(argv[2], "sbe") == 0) {
204*4882a593Smuzhiyun val |= ECC_ERROR_DETECT_SBE;
205*4882a593Smuzhiyun } else if (strcmp(argv[2], "mbe") == 0) {
206*4882a593Smuzhiyun val |= ECC_ERROR_DETECT_MBE;
207*4882a593Smuzhiyun } else if (strcmp(argv[2], "mse") == 0) {
208*4882a593Smuzhiyun val |= ECC_ERROR_DETECT_MSE;
209*4882a593Smuzhiyun } else if (strcmp(argv[2], "all") == 0) {
210*4882a593Smuzhiyun val |= (ECC_ERROR_DETECT_MME |
211*4882a593Smuzhiyun ECC_ERROR_DETECT_MBE |
212*4882a593Smuzhiyun ECC_ERROR_DETECT_SBE |
213*4882a593Smuzhiyun ECC_ERROR_DETECT_MSE);
214*4882a593Smuzhiyun } else {
215*4882a593Smuzhiyun printf("Incorrect err_detect field\n");
216*4882a593Smuzhiyun return 1;
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun ddr->err_detect = val;
220*4882a593Smuzhiyun return 0;
221*4882a593Smuzhiyun } else if (strcmp(argv[1], "injectdatahi") == 0) {
222*4882a593Smuzhiyun val = simple_strtoul(argv[2], NULL, 16);
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun ddr->data_err_inject_hi = val;
225*4882a593Smuzhiyun return 0;
226*4882a593Smuzhiyun } else if (strcmp(argv[1], "injectdatalo") == 0) {
227*4882a593Smuzhiyun val = simple_strtoul(argv[2], NULL, 16);
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun ddr->data_err_inject_lo = val;
230*4882a593Smuzhiyun return 0;
231*4882a593Smuzhiyun } else if (strcmp(argv[1], "injectecc") == 0) {
232*4882a593Smuzhiyun val = simple_strtoul(argv[2], NULL, 16);
233*4882a593Smuzhiyun if (val > 0xff) {
234*4882a593Smuzhiyun printf("Incorrect ECC inject mask, "
235*4882a593Smuzhiyun "should be 0x00..0xff\n");
236*4882a593Smuzhiyun return 1;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun ddr->ecc_err_inject = val;
241*4882a593Smuzhiyun return 0;
242*4882a593Smuzhiyun } else if (strcmp(argv[1], "inject") == 0) {
243*4882a593Smuzhiyun val = ddr->ecc_err_inject;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun if (strcmp(argv[2], "en") == 0)
246*4882a593Smuzhiyun val |= ECC_ERR_INJECT_EIEN;
247*4882a593Smuzhiyun else if (strcmp(argv[2], "dis") == 0)
248*4882a593Smuzhiyun val &= ~ECC_ERR_INJECT_EIEN;
249*4882a593Smuzhiyun else
250*4882a593Smuzhiyun printf("Incorrect command\n");
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun ddr->ecc_err_inject = val;
253*4882a593Smuzhiyun __asm__ __volatile__("sync");
254*4882a593Smuzhiyun __asm__ __volatile__("isync");
255*4882a593Smuzhiyun return 0;
256*4882a593Smuzhiyun } else if (strcmp(argv[1], "mirror") == 0) {
257*4882a593Smuzhiyun val = ddr->ecc_err_inject;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun if (strcmp(argv[2], "en") == 0)
260*4882a593Smuzhiyun val |= ECC_ERR_INJECT_EMB;
261*4882a593Smuzhiyun else if (strcmp(argv[2], "dis") == 0)
262*4882a593Smuzhiyun val &= ~ECC_ERR_INJECT_EMB;
263*4882a593Smuzhiyun else
264*4882a593Smuzhiyun printf("Incorrect command\n");
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun ddr->ecc_err_inject = val;
267*4882a593Smuzhiyun return 0;
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun if (argc == 4) {
271*4882a593Smuzhiyun if (strcmp(argv[1], "testdw") == 0) {
272*4882a593Smuzhiyun addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
273*4882a593Smuzhiyun count = simple_strtoul(argv[3], NULL, 16);
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun if ((u32) addr % 8) {
276*4882a593Smuzhiyun printf("Address not aligned on "
277*4882a593Smuzhiyun "double word boundary\n");
278*4882a593Smuzhiyun return 1;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun disable_interrupts();
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun for (i = addr; i < addr + count; i++) {
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun /* enable injects */
285*4882a593Smuzhiyun ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
286*4882a593Smuzhiyun __asm__ __volatile__("sync");
287*4882a593Smuzhiyun __asm__ __volatile__("isync");
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun /* write memory location injecting errors */
290*4882a593Smuzhiyun ppcDWstore((u32 *) i, pattern);
291*4882a593Smuzhiyun __asm__ __volatile__("sync");
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun /* disable injects */
294*4882a593Smuzhiyun ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
295*4882a593Smuzhiyun __asm__ __volatile__("sync");
296*4882a593Smuzhiyun __asm__ __volatile__("isync");
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun /* read data, this generates ECC error */
299*4882a593Smuzhiyun ppcDWload((u32 *) i, ret);
300*4882a593Smuzhiyun __asm__ __volatile__("sync");
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun /* re-initialize memory, double word write the location again,
303*4882a593Smuzhiyun * generates new ECC code this time */
304*4882a593Smuzhiyun ppcDWstore((u32 *) i, writeback);
305*4882a593Smuzhiyun __asm__ __volatile__("sync");
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun enable_interrupts();
308*4882a593Smuzhiyun return 0;
309*4882a593Smuzhiyun }
310*4882a593Smuzhiyun if (strcmp(argv[1], "testword") == 0) {
311*4882a593Smuzhiyun addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
312*4882a593Smuzhiyun count = simple_strtoul(argv[3], NULL, 16);
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun if ((u32) addr % 8) {
315*4882a593Smuzhiyun printf("Address not aligned on "
316*4882a593Smuzhiyun "double word boundary\n");
317*4882a593Smuzhiyun return 1;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun disable_interrupts();
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun for (i = addr; i < addr + count; i++) {
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun /* enable injects */
324*4882a593Smuzhiyun ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
325*4882a593Smuzhiyun __asm__ __volatile__("sync");
326*4882a593Smuzhiyun __asm__ __volatile__("isync");
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun /* write memory location injecting errors */
329*4882a593Smuzhiyun *(u32 *) i = 0xfedcba98UL;
330*4882a593Smuzhiyun __asm__ __volatile__("sync");
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun /* sub double word write,
333*4882a593Smuzhiyun * bus will read-modify-write,
334*4882a593Smuzhiyun * generates ECC error */
335*4882a593Smuzhiyun *((u32 *) i + 1) = 0x76543210UL;
336*4882a593Smuzhiyun __asm__ __volatile__("sync");
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun /* disable injects */
339*4882a593Smuzhiyun ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
340*4882a593Smuzhiyun __asm__ __volatile__("sync");
341*4882a593Smuzhiyun __asm__ __volatile__("isync");
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun /* re-initialize memory,
344*4882a593Smuzhiyun * double word write the location again,
345*4882a593Smuzhiyun * generates new ECC code this time */
346*4882a593Smuzhiyun ppcDWstore((u32 *) i, writeback);
347*4882a593Smuzhiyun __asm__ __volatile__("sync");
348*4882a593Smuzhiyun }
349*4882a593Smuzhiyun enable_interrupts();
350*4882a593Smuzhiyun return 0;
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun return cmd_usage(cmdtp);
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun U_BOOT_CMD(ecc, 4, 0, do_ecc,
357*4882a593Smuzhiyun "support for DDR ECC features",
358*4882a593Smuzhiyun "status - print out status info\n"
359*4882a593Smuzhiyun "ecc captureclear - clear capture regs data\n"
360*4882a593Smuzhiyun "ecc sbecnt <val> - set Single-Bit Error counter\n"
361*4882a593Smuzhiyun "ecc sbethr <val> - set Single-Bit Threshold\n"
362*4882a593Smuzhiyun "ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n"
363*4882a593Smuzhiyun " [-|+]sbe - Single-Bit Error\n"
364*4882a593Smuzhiyun " [-|+]mbe - Multiple-Bit Error\n"
365*4882a593Smuzhiyun " [-|+]mse - Memory Select Error\n"
366*4882a593Smuzhiyun " [-|+]all - all errors\n"
367*4882a593Smuzhiyun "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
368*4882a593Smuzhiyun " mme - Multiple Memory Errors\n"
369*4882a593Smuzhiyun " sbe - Single-Bit Error\n"
370*4882a593Smuzhiyun " mbe - Multiple-Bit Error\n"
371*4882a593Smuzhiyun " mse - Memory Select Error\n"
372*4882a593Smuzhiyun " all - all errors\n"
373*4882a593Smuzhiyun "ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n"
374*4882a593Smuzhiyun "ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n"
375*4882a593Smuzhiyun "ecc injectecc <ecc> - set ECC Error Injection Mask\n"
376*4882a593Smuzhiyun "ecc inject <en|dis> - enable/disable error injection\n"
377*4882a593Smuzhiyun "ecc mirror <en|dis> - enable/disable mirror byte\n"
378*4882a593Smuzhiyun "ecc testdw <addr> <cnt> - test mem region with double word access:\n"
379*4882a593Smuzhiyun " - enables injects\n"
380*4882a593Smuzhiyun " - writes pattern injecting errors with double word access\n"
381*4882a593Smuzhiyun " - disables injects\n"
382*4882a593Smuzhiyun " - reads pattern back with double word access, generates error\n"
383*4882a593Smuzhiyun " - re-inits memory\n"
384*4882a593Smuzhiyun "ecc testword <addr> <cnt> - test mem region with word access:\n"
385*4882a593Smuzhiyun " - enables injects\n"
386*4882a593Smuzhiyun " - writes pattern injecting errors with word access\n"
387*4882a593Smuzhiyun " - writes pattern with word access, generates error\n"
388*4882a593Smuzhiyun " - disables injects\n" " - re-inits memory");
389*4882a593Smuzhiyun #endif
390