1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <ns16550.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <nand.h>
11*4882a593Smuzhiyun #include <linux/compiler.h>
12*4882a593Smuzhiyun #include <asm/fsl_law.h>
13*4882a593Smuzhiyun #include <fsl_ddr_sdram.h>
14*4882a593Smuzhiyun #include <asm/global_data.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /*
19*4882a593Smuzhiyun * Fixed sdram init -- doesn't use serial presence detect.
20*4882a593Smuzhiyun */
sdram_init(void)21*4882a593Smuzhiyun static void sdram_init(void)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun struct ccsr_ddr __iomem *ddr =
24*4882a593Smuzhiyun (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
27*4882a593Smuzhiyun __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
28*4882a593Smuzhiyun #if CONFIG_CHIP_SELECTS_PER_CTRL > 1
29*4882a593Smuzhiyun __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
30*4882a593Smuzhiyun __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
31*4882a593Smuzhiyun #endif
32*4882a593Smuzhiyun __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
33*4882a593Smuzhiyun __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
34*4882a593Smuzhiyun __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
35*4882a593Smuzhiyun __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
38*4882a593Smuzhiyun __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
39*4882a593Smuzhiyun __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
42*4882a593Smuzhiyun __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
43*4882a593Smuzhiyun __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
46*4882a593Smuzhiyun __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
47*4882a593Smuzhiyun __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
48*4882a593Smuzhiyun __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* Set, but do not enable the memory */
51*4882a593Smuzhiyun __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun asm volatile("sync;isync");
54*4882a593Smuzhiyun udelay(500);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* Let the controller go */
57*4882a593Smuzhiyun out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
board_init_f(ulong bootflag)62*4882a593Smuzhiyun void board_init_f(ulong bootflag)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun u32 plat_ratio;
65*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* initialize selected port with appropriate baud rate */
68*4882a593Smuzhiyun plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
69*4882a593Smuzhiyun plat_ratio >>= 1;
70*4882a593Smuzhiyun gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
73*4882a593Smuzhiyun gd->bus_clk / 16 / CONFIG_BAUDRATE);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun puts("\nNAND boot... ");
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* Initialize the DDR3 */
78*4882a593Smuzhiyun sdram_init();
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /* copy code to RAM and jump to it - this should not return */
81*4882a593Smuzhiyun /* NOTE - code has to be copied out of NAND buffer before
82*4882a593Smuzhiyun * other blocks can be read.
83*4882a593Smuzhiyun */
84*4882a593Smuzhiyun relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
board_init_r(gd_t * gd,ulong dest_addr)87*4882a593Smuzhiyun void board_init_r(gd_t *gd, ulong dest_addr)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun nand_boot();
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
putc(char c)92*4882a593Smuzhiyun void putc(char c)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun if (c == '\n')
95*4882a593Smuzhiyun NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
puts(const char * str)100*4882a593Smuzhiyun void puts(const char *str)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun while (*str)
103*4882a593Smuzhiyun putc(*str++);
104*4882a593Smuzhiyun }
105