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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/fpga/
H A Daltera-hps2fpga-bridge.txt17 reg = <0xff400000 0x100000>;
20 bridge-enable = <0>;
25 reg = <0xff500000 0x10000>;
33 reg = <0xff600000 0x100000>;
H A Dfpga-region.txt210 bridge's region (0xff200000) and the hps bridge's region (0xc0000000) for use by
218 reg = <0xff706000 0x1000
219 0xffb90000 0x20>;
220 interrupts = <0 175 4>;
225 reg = <0xff400000 0x100000>;
241 reg = <0xff500000 0x10000>;
250 fragment@0 {
260 ranges = <0x20000 0xff200000 0x100000>,
261 <0x0 0xc0000000 0x20000000>;
265 reg = <0x10040 0x20>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dbase_addr_ac5.h10 #define SOCFPGA_STM_ADDRESS 0xfc000000
11 #define SOCFPGA_DAP_ADDRESS 0xff000000
12 #define SOCFPGA_EMAC0_ADDRESS 0xff700000
13 #define SOCFPGA_EMAC1_ADDRESS 0xff702000
14 #define SOCFPGA_SDMMC_ADDRESS 0xff704000
15 #define SOCFPGA_QSPI_ADDRESS 0xff705000
16 #define SOCFPGA_GPIO0_ADDRESS 0xff708000
17 #define SOCFPGA_GPIO1_ADDRESS 0xff709000
18 #define SOCFPGA_GPIO2_ADDRESS 0xff70a000
19 #define SOCFPGA_L3REGS_ADDRESS 0xff800000
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Drockchip,rk3308-cru.txt42 reg = <0x0 0xff500000 0x0 0x1000>;
53 reg = <0x0 0xff0a0000 0x0 0x100>;
H A Drockchip,rk3308.txt40 reg = <0x0 0xff500000 0x0 0x1000>;
51 reg = <0x0 0xff0a0000 0x0 0x100>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/usb/
H A Damlogic,meson-g12a-usb-ctrl.yaml81 "^usb@[0-9a-f]+$":
199 reg = <0xffe09000 0xa0>;
215 reg = <0xff400000 0x40000>;
228 reg = <0xff500000 0x100000>;
/OK3568_Linux_fs/kernel/drivers/mtd/maps/
H A Dichxrom.c30 #define BIOS_CNTL 0x4e
31 #define FWH_DEC_EN1 0xE3
32 #define FWH_DEC_EN2 0xF0
33 #define FWH_SEL1 0xE8
34 #define FWH_SEL2 0xEE
83 window->phys = 0; in ichxrom_cleanup()
84 window->size = 0; in ichxrom_cleanup()
113 window->phys = 0; in ichxrom_init_one()
115 if (byte == 0xff) { in ichxrom_init_one()
116 window->phys = 0xffc00000; in ichxrom_init_one()
[all …]
H A Desb2rom.c34 #define BIOS_CNTL 0xDC
35 #define BIOS_LOCK_ENABLE 0x02
36 #define BIOS_WRITE_ENABLE 0x01
39 #define FWH_DEC_EN1 0xD8
40 #define FWH_F8_EN 0x8000
41 #define FWH_F0_EN 0x4000
42 #define FWH_E8_EN 0x2000
43 #define FWH_E0_EN 0x1000
44 #define FWH_D8_EN 0x0800
45 #define FWH_D0_EN 0x0400
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3308/
H A Drk3308.c27 .virt = 0x0UL,
28 .phys = 0x0UL,
29 .size = 0xff000000UL,
33 .virt = 0xff000000UL,
34 .phys = 0xff000000UL,
35 .size = 0x01000000UL,
41 0,
48 #define GRF_BASE 0xff000000
49 #define SGRF_BASE 0xff2b0000
50 #define CRU_BASE 0xff500000
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399pro-npu.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0x0 0x0>;
50 reg = <0x0 0x1>;
115 #clock-cells = <0>;
122 #clock-cells = <0>;
124 pinctrl-0 = <&clkin_32k>;
145 reg = <0x0 0xfd000000 0x0 0x200000>;
165 reg = <0x0 0xfe000000 0x0 0x1000>;
180 reg = <0x0 0xfe010000 0x0 0x8000>;
[all …]
H A Drk3368.dtsi43 #address-cells = <0x2>;
44 #size-cells = <0x0>;
78 cpu_l0: cpu@0 {
81 reg = <0x0 0x0>;
89 reg = <0x0 0x1>;
97 reg = <0x0 0x2>;
105 reg = <0x0 0x3>;
113 reg = <0x0 0x100>;
121 reg = <0x0 0x101>;
129 reg = <0x0 0x102>;
[all …]
/OK3568_Linux_fs/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3308.c27 #define CRU_BASE 0xff500000
28 #define GRF_BASE 0xff000000
29 #define SGRF_BASE 0xff2b0000
30 #define DDR_PHY_BASE 0xff530000
31 #define DDR_PCTL_BASE 0xff010000
32 #define DDR_STANDBY_BASE 0xff030000
33 #define PMU_BASS_ADDR 0xff520000
34 #define SERVICE_MSCH_BASE 0xff5c8000
136 rk3308_pll_div.frac = 0x872B02; in rkdclk_init()
137 rk3308_pll_div.dsmpd = 0; in rkdclk_init()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drv1126.dtsi46 #size-cells = <0>;
51 reg = <0xf00>;
61 reg = <0xf01>;
71 reg = <0xf02>;
81 reg = <0xf03>;
94 arm,psci-suspend-param = <0x0010000>;
164 bus-id = <0>;
165 cfg-val = <0x00300020>;
166 enable-msk = <0x7144>;
171 cfg-val = <0x00300020>;
[all …]
H A Drk3308.dtsi35 #size-cells = <0>;
37 cpu0: cpu@0 {
40 reg = <0x0 0x0>;
47 reg = <0x0 0x1>;
54 reg = <0x0 0x2>;
61 reg = <0x0 0x3>;
79 #clock-cells = <0>;
101 reg = <0x0 0xff010000 0x0 0x10000>;
121 #clock-cells = <0>;
129 reg = <0x0 0xff000000 0x0 0x10000>;
[all …]
H A Drk3368.dtsi76 #address-cells = <0x2>;
77 #size-cells = <0x0>;
114 cpu_sleep: cpu-sleep-0 {
116 arm,psci-suspend-param = <0x1010000>;
117 entry-latency-us = <0x3fffffff>;
118 exit-latency-us = <0x40000000>;
119 min-residency-us = <0xffffffff>;
123 cpu_l0: cpu@0 {
126 reg = <0x0 0x0>;
136 reg = <0x0 0x1>;
[all …]
H A D.rk3368-sheep.dtb.dts.tmp
H A D.rk3368-geekbox.dtb.dts.tmp
H A D.rk3368-lion.dtb.dts.tmp
H A Drv1106.dtsi55 #size-cells = <0>;
60 reg = <0xf00>;
106 rockchip,wake-irq = <0>;
107 rockchip,irq-mode-enable = <0>;
133 size = <0x800000>;
211 thermal-sensors = <&tsadc 0>;
213 threshold: trip-point-0 {
244 #clock-cells = <0>;
249 reg = <0xff000000 0x68000>;
258 offset = <0x20200>;
[all …]
H A D.rk3368-px5-evb.dtb.dts.tmp
H A D.rk3308-evb.dtb.dts.tmp
H A Drk3328.dtsi35 #size-cells = <0>;
37 cpu0: cpu@0 {
40 reg = <0x0 0x0>;
48 reg = <0x0 0x1>;
54 reg = <0x0 0x2>;
60 reg = <0x0 0x3>;
126 #clock-cells = <0>;
133 reg = <0x0 0xff000000 0x0 0x1000>;
145 reg = <0x0 0xff010000 0x0 0x1000>;
157 reg = <0x0 0xff020000 0x0 0x1000>;
[all …]
H A Drk3288.dtsi55 #size-cells = <0>;
62 reg = <0x500>;
87 reg = <0x501>;
93 reg = <0x502>;
99 reg = <0x503>;
113 reg = <0xff250000 0x4000>;
124 reg = <0xff600000 0x4000>;
125 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
136 reg = <0xffb20000 0x4000>;
137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dsocfpga.dtsi23 #size-cells = <0>;
26 cpu0: cpu@0 {
29 reg = <0>;
43 interrupts = <0 176 4>, <0 177 4>;
45 reg = <0xff111000 0x1000>,
46 <0xff113000 0x1000>;
53 reg = <0xfffed000 0x1000>,
54 <0xfffec100 0x100>;
73 reg = <0xffe01000 0x1000>;
74 interrupts = <0 104 4>,
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/amlogic/
H A Dmeson-axg.dtsi23 tdmif_a: audio-controller-0 {
25 #sound-dai-cells = <0>;
36 #sound-dai-cells = <0>;
47 #sound-dai-cells = <0>;
66 #address-cells = <0x2>;
67 #size-cells = <0x0>;
69 cpu0: cpu@0 {
72 reg = <0x0 0x0>;
75 clocks = <&scpi_dvfs 0>;
81 reg = <0x0 0x1>;
[all …]

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