1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. 3 4#include <dt-bindings/clock/rk1808-cru.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/pinctrl/rockchip.h> 8#include <dt-bindings/power/rk1808-power.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/thermal/thermal.h> 11 12/ { 13 compatible = "rockchip,rk3399pro-npu"; 14 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 serial2 = &uart2; 23 }; 24 25 cpus { 26 #address-cells = <2>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a35", "arm,armv8"; 32 reg = <0x0 0x0>; 33 enable-method = "psci"; 34 clocks = <&cru ARMCLK>; 35 operating-points-v2 = <&cpu0_opp_table>; 36 dynamic-power-coefficient = <74>; 37 #cooling-cells = <2>; 38 power-model { 39 compatible = "simple-power-model"; 40 ref-leakage = <31>; 41 static-coefficient = <100000>; 42 ts = <597400 241050 (-2450) 70>; 43 thermal-zone = "soc-thermal"; 44 }; 45 }; 46 47 cpu1: cpu@1 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a35", "arm,armv8"; 50 reg = <0x0 0x1>; 51 enable-method = "psci"; 52 clocks = <&cru ARMCLK>; 53 operating-points-v2 = <&cpu0_opp_table>; 54 dynamic-power-coefficient = <74>; 55 }; 56 }; 57 58 cpu0_opp_table: cpu0-opp-table { 59 compatible = "operating-points-v2"; 60 opp-shared; 61 62 opp-408000000 { 63 opp-hz = /bits/ 64 <408000000>; 64 opp-microvolt = <750000 750000 950000>; 65 clock-latency-ns = <40000>; 66 opp-suspend; 67 }; 68 opp-600000000 { 69 opp-hz = /bits/ 64 <600000000>; 70 opp-microvolt = <750000 750000 950000>; 71 clock-latency-ns = <40000>; 72 }; 73 opp-816000000 { 74 opp-hz = /bits/ 64 <816000000>; 75 opp-microvolt = <750000 750000 950000>; 76 clock-latency-ns = <40000>; 77 }; 78 opp-1008000000 { 79 opp-hz = /bits/ 64 <1008000000>; 80 opp-microvolt = <750000 750000 950000>; 81 clock-latency-ns = <40000>; 82 }; 83 opp-1200000000 { 84 opp-hz = /bits/ 64 <1200000000>; 85 opp-microvolt = <750000 750000 950000>; 86 clock-latency-ns = <40000>; 87 }; 88 }; 89 90 arm-pmu { 91 compatible = "arm,cortex-a53-pmu"; 92 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 94 interrupt-affinity = <&cpu0>, <&cpu1>; 95 }; 96 97 psci { 98 compatible = "arm,psci-1.0"; 99 method = "smc"; 100 }; 101 102 timer { 103 compatible = "arm,armv8-timer"; 104 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 105 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 106 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 107 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 108 arm,no-tick-in-suspend; 109 }; 110 111 xin24m: xin24m { 112 compatible = "fixed-clock"; 113 clock-frequency = <24000000>; 114 clock-output-names = "xin24m"; 115 #clock-cells = <0>; 116 }; 117 118 xin32k: xin32k { 119 compatible = "fixed-clock"; 120 clock-frequency = <32768>; 121 clock-output-names = "xin32k"; 122 #clock-cells = <0>; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&clkin_32k>; 125 }; 126 127 usbdrd3: usb { 128 compatible = "rockchip,rk1808-dwc3", "rockchip,rk3399-dwc3"; 129 clocks = <&cru SCLK_USB3_OTG0_REF>, <&cru ACLK_USB3OTG>, 130 <&cru SCLK_USB3_OTG0_SUSPEND>; 131 clock-names = "ref_clk", "bus_clk", 132 "suspend_clk"; 133 assigned-clocks = <&cru SCLK_USB3_OTG0_SUSPEND>; 134 assigned-clock-rates = <24000000>; 135 power-domains = <&power RK1808_PD_PCIE>; 136 resets = <&cru SRST_USB3_OTG_A>; 137 reset-names = "usb3-otg"; 138 #address-cells = <2>; 139 #size-cells = <2>; 140 ranges; 141 status = "disabled"; 142 143 usbdrd_dwc3: dwc3@fd000000 { 144 compatible = "snps,dwc3"; 145 reg = <0x0 0xfd000000 0x0 0x200000>; 146 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 147 dr_mode = "peripheral"; 148 phys = <&u2phy_otg>, <&combphy PHY_TYPE_USB3>; 149 phy-names = "usb2-phy", "usb3-phy"; 150 phy_type = "utmi_wide"; 151 snps,dis_enblslpm_quirk; 152 snps,dis-u1u2-quirk; 153 snps,dis-u2-freeclk-exists-quirk; 154 snps,dis_u2_susphy_quirk; 155 snps,dis_u3_susphy_quirk; 156 snps,dis-del-phy-power-chg-quirk; 157 snps,tx-ipgap-linecheck-dis-quirk; 158 snps,xhci-trb-ent-quirk; 159 status = "disabled"; 160 }; 161 }; 162 163 grf: syscon@fe000000 { 164 compatible = "rockchip,rk1808-grf", "syscon", "simple-mfd"; 165 reg = <0x0 0xfe000000 0x0 0x1000>; 166 #address-cells = <1>; 167 #size-cells = <1>; 168 169 npu_pvtm: npu-pvtm { 170 compatible = "rockchip,rk1808-npu-pvtm"; 171 clocks = <&cru SCLK_PVTM_NPU>; 172 clock-names = "npu"; 173 status = "okay"; 174 }; 175 }; 176 177 usb2phy_grf: syscon@fe010000 { 178 compatible = "rockchip,rk1808-usb2phy-grf", "syscon", 179 "simple-mfd"; 180 reg = <0x0 0xfe010000 0x0 0x8000>; 181 #address-cells = <1>; 182 #size-cells = <1>; 183 184 u2phy: usb2-phy@100 { 185 compatible = "rockchip,rk1808-usb2phy"; 186 reg = <0x100 0x10>; 187 clocks = <&cru SCLK_USBPHY_REF>; 188 clock-names = "phyclk"; 189 #clock-cells = <0>; 190 assigned-clocks = <&cru USB480M>; 191 assigned-clock-parents = <&u2phy>; 192 clock-output-names = "usb480m_phy"; 193 status = "disabled"; 194 195 u2phy_host: host-port { 196 #phy-cells = <0>; 197 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 198 interrupt-names = "linestate"; 199 status = "disabled"; 200 }; 201 202 u2phy_otg: otg-port { 203 #phy-cells = <0>; 204 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 207 interrupt-names = "otg-bvalid", "otg-id", 208 "linestate"; 209 status = "disabled"; 210 }; 211 }; 212 }; 213 214 combphy_grf: syscon@fe018000 { 215 compatible = "rockchip,usb3phy-grf", "syscon"; 216 reg = <0x0 0xfe018000 0x0 0x8000>; 217 }; 218 219 pmugrf: syscon@fe020000 { 220 compatible = "rockchip,rk1808-pmugrf", "syscon", "simple-mfd"; 221 reg = <0x0 0xfe020000 0x0 0x1000>; 222 #address-cells = <1>; 223 #size-cells = <1>; 224 225 pmu_pvtm: pmu-pvtm { 226 compatible = "rockchip,rk1808-pmu-pvtm"; 227 clocks = <&cru SCLK_PVTM_PMU>; 228 clock-names = "pmu"; 229 status = "okay"; 230 }; 231 }; 232 233 usb_pcie_grf: syscon@fe040000 { 234 compatible = "rockchip,usb-pcie-grf", "syscon"; 235 reg = <0x0 0xfe040000 0x0 0x1000>; 236 }; 237 238 coregrf: syscon@fe050000 { 239 compatible = "rockchip,rk1808-coregrf", "syscon", "simple-mfd"; 240 reg = <0x0 0xfe050000 0x0 0x1000>; 241 #address-cells = <1>; 242 #size-cells = <1>; 243 244 pvtm: pvtm { 245 compatible = "rockchip,rk1808-pvtm"; 246 clocks = <&cru SCLK_PVTM_CORE>; 247 clock-names = "core"; 248 status = "okay"; 249 }; 250 }; 251 252 qos_npu: qos@fe850000 { 253 compatible = "syscon"; 254 reg = <0x0 0xfe850000 0x0 0x20>; 255 }; 256 257 qos_pcie: qos@fe880000 { 258 compatible = "syscon"; 259 reg = <0x0 0xfe880000 0x0 0x20>; 260 status = "disabled"; 261 }; 262 263 qos_usb2: qos@fe890000 { 264 compatible = "syscon"; 265 reg = <0x0 0xfe890000 0x0 0x20>; 266 status = "disabled"; 267 }; 268 269 qos_usb3: qos@fe890080 { 270 compatible = "syscon"; 271 reg = <0x0 0xfe890080 0x0 0x20>; 272 status = "disabled"; 273 }; 274 275 qos_isp: qos@fe8a0000 { 276 compatible = "syscon"; 277 reg = <0x0 0xfe8a0000 0x0 0x20>; 278 }; 279 280 qos_rga_rd: qos@fe8a0080 { 281 compatible = "syscon"; 282 reg = <0x0 0xfe8a0080 0x0 0x20>; 283 }; 284 285 qos_rga_wr: qos@fe8a0100 { 286 compatible = "syscon"; 287 reg = <0x0 0xfe8a0100 0x0 0x20>; 288 }; 289 290 qos_cif: qos@fe8a0180 { 291 compatible = "syscon"; 292 reg = <0x0 0xfe8a0180 0x0 0x20>; 293 }; 294 295 qos_vop_raw: qos@fe8b0000 { 296 compatible = "syscon"; 297 reg = <0x0 0xfe8b0000 0x0 0x20>; 298 }; 299 300 qos_vop_lite: qos@fe8b0080 { 301 compatible = "syscon"; 302 reg = <0x0 0xfe8b0080 0x0 0x20>; 303 }; 304 305 qos_vpu: qos@fe8c0000 { 306 compatible = "syscon"; 307 reg = <0x0 0xfe8c0000 0x0 0x20>; 308 }; 309 310 gic: interrupt-controller@ff100000 { 311 compatible = "arm,gic-v3"; 312 #interrupt-cells = <3>; 313 #address-cells = <2>; 314 #size-cells = <2>; 315 ranges; 316 interrupt-controller; 317 318 reg = <0x0 0xff100000 0 0x10000>, /* GICD */ 319 <0x0 0xff140000 0 0xc0000>, /* GICR */ 320 <0x0 0xff300000 0 0x10000>, /* GICC */ 321 <0x0 0xff310000 0 0x10000>, /* GICH */ 322 <0x0 0xff320000 0 0x10000>; /* GICV */ 323 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 324 its: interrupt-controller@ff120000 { 325 compatible = "arm,gic-v3-its"; 326 msi-controller; 327 reg = <0x0 0xff120000 0x0 0x20000>; 328 }; 329 }; 330 331 cru: clock-controller@ff350000 { 332 compatible = "rockchip,rk1808-cru"; 333 reg = <0x0 0xff350000 0x0 0x5000>; 334 rockchip,grf = <&grf>; 335 #clock-cells = <1>; 336 #reset-cells = <1>; 337 338 assigned-clocks = 339 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 340 <&cru PLL_PPLL>, <&cru ARMCLK>, 341 <&cru MSCLK_PERI>, <&cru LSCLK_PERI>, 342 <&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>, 343 <&cru LSCLK_BUS_PRE>; 344 assigned-clock-rates = 345 <1188000000>, <1000000000>, 346 <100000000>, <1200000000>, 347 <200000000>, <100000000>, 348 <300000000>, <200000000>, 349 <100000000>; 350 }; 351 352 combphy: phy@ff380000 { 353 compatible = "rockchip,rk1808-combphy"; 354 reg = <0x0 0xff380000 0x0 0x10000>; 355 #phy-cells = <1>; 356 clocks = <&cru SCLK_PCIEPHY_REF>; 357 clock-names = "refclk"; 358 assigned-clocks = <&cru SCLK_PCIEPHY_REF>; 359 assigned-clock-rates = <25000000>; 360 resets = <&cru SRST_USB3_OTG_A>, <&cru SRST_PCIEPHY_POR>, 361 <&cru SRST_PCIEPHY_P>, <&cru SRST_PCIEPHY_PIPE>; 362 reset-names = "otg-rst", "combphy-por", 363 "combphy-apb", "combphy-pipe"; 364 rockchip,combphygrf = <&combphy_grf>; 365 rockchip,usbpciegrf = <&usb_pcie_grf>; 366 status = "disabled"; 367 }; 368 369 thermal_zones: thermal-zones { 370 soc_thermal: soc-thermal { 371 polling-delay-passive = <20>; /* milliseconds */ 372 polling-delay = <1000>; /* milliseconds */ 373 sustainable-power = <977>; /* milliwatts */ 374 375 thermal-sensors = <&tsadc 0>; 376 377 trips { 378 threshold: trip-point-0 { 379 /* millicelsius */ 380 temperature = <75000>; 381 /* millicelsius */ 382 hysteresis = <2000>; 383 type = "passive"; 384 }; 385 target: trip-point-1 { 386 /* millicelsius */ 387 temperature = <85000>; 388 /* millicelsius */ 389 hysteresis = <2000>; 390 type = "passive"; 391 }; 392 soc_crit: soc-crit { 393 /* millicelsius */ 394 temperature = <115000>; 395 /* millicelsius */ 396 hysteresis = <2000>; 397 type = "critical"; 398 }; 399 }; 400 401 cooling-maps { 402 map0 { 403 trip = <&target>; 404 cooling-device = 405 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 406 contribution = <4096>; 407 }; 408 map1 { 409 trip = <&target>; 410 cooling-device = 411 <&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 412 contribution = <1024>; 413 }; 414 }; 415 }; 416 }; 417 418 tsadc: tsadc@ff3a0000 { 419 compatible = "rockchip,rk1808-tsadc"; 420 reg = <0x0 0xff3a0000 0x0 0x100>; 421 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 422 rockchip,grf = <&grf>; 423 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 424 clock-names = "tsadc", "apb_pclk"; 425 assigned-clocks = <&cru SCLK_TSADC>; 426 assigned-clock-rates = <650000>; 427 resets = <&cru SRST_TSADC>; 428 reset-names = "tsadc-apb"; 429 #thermal-sensor-cells = <1>; 430 rockchip,hw-tshut-temp = <120000>; 431 status = "disabled"; 432 }; 433 434 pmu: power-management@ff3e0000 { 435 compatible = "rockchip,rk1808-pmu", "syscon", "simple-mfd"; 436 reg = <0x0 0xff3e0000 0x0 0x1000>; 437 438 power: power-controller { 439 compatible = "rockchip,rk1808-power-controller"; 440 #power-domain-cells = <1>; 441 #address-cells = <1>; 442 #size-cells = <0>; 443 status = "okay"; 444 445 /* These power domains are grouped by VD_NPU */ 446 pd_npu@RK1808_VD_NPU { 447 reg = <RK1808_VD_NPU>; 448 clocks = <&cru SCLK_NPU>, 449 <&cru ACLK_NPU>, 450 <&cru HCLK_NPU>; 451 pm_qos = <&qos_npu>; 452 }; 453 454 /* These power domains are grouped by VD_LOGIC */ 455 pd_pcie@RK1808_PD_PCIE { 456 reg = <RK1808_PD_PCIE>; 457 clocks = <&cru HSCLK_PCIE>, 458 <&cru LSCLK_PCIE>, 459 <&cru ACLK_PCIE>, 460 <&cru ACLK_PCIE_MST>, 461 <&cru ACLK_PCIE_SLV>, 462 <&cru PCLK_PCIE>, 463 <&cru SCLK_PCIE_AUX>, 464 <&cru SCLK_PCIE_AUX>, 465 <&cru ACLK_USB3OTG>, 466 <&cru HCLK_HOST>, 467 <&cru HCLK_HOST_ARB>, 468 <&cru SCLK_USB3_OTG0_REF>, 469 <&cru SCLK_USB3_OTG0_SUSPEND>; 470 pm_qos = <&qos_pcie>, 471 <&qos_usb2>, 472 <&qos_usb3>; 473 }; 474 pd_vpu@RK1808_PD_VPU { 475 reg = <RK1808_PD_VPU>; 476 clocks = <&cru ACLK_VPU>, 477 <&cru HCLK_VPU>; 478 pm_qos = <&qos_vpu>; 479 }; 480 pd_vio@RK1808_PD_VIO { 481 reg = <RK1808_PD_VIO>; 482 clocks = <&cru HSCLK_VIO>, 483 <&cru LSCLK_VIO>, 484 <&cru ACLK_VOPRAW>, 485 <&cru HCLK_VOPRAW>, 486 <&cru ACLK_VOPLITE>, 487 <&cru HCLK_VOPLITE>, 488 <&cru PCLK_DSI_TX>, 489 <&cru PCLK_CSI_TX>, 490 <&cru ACLK_RGA>, 491 <&cru HCLK_RGA>, 492 <&cru ACLK_ISP>, 493 <&cru HCLK_ISP>, 494 <&cru ACLK_CIF>, 495 <&cru HCLK_CIF>, 496 <&cru PCLK_CSI2HOST>, 497 <&cru DCLK_VOPRAW>, 498 <&cru DCLK_VOPLITE>; 499 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 500 <&qos_isp>, <&qos_cif>, 501 <&qos_vop_raw>, <&qos_vop_lite>; 502 }; 503 }; 504 }; 505 506 i2c0: i2c@ff410000 { 507 compatible = "rockchip,rk3399-i2c"; 508 reg = <0x0 0xff410000 0x0 0x1000>; 509 clocks = <&cru SCLK_PMU_I2C0>, <&cru PCLK_I2C0_PMU>; 510 clock-names = "i2c", "pclk"; 511 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 512 pinctrl-names = "default"; 513 pinctrl-0 = <&i2c0_xfer>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 status = "disabled"; 517 }; 518 519 dmac: dmac@ff4e0000 { 520 compatible = "arm,pl330", "arm,primecell"; 521 reg = <0x0 0xff4e0000 0x0 0x4000>; 522 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&cru ACLK_DMAC>; 524 clock-names = "apb_pclk"; 525 #dma-cells = <1>; 526 arm,pl330-periph-burst; 527 }; 528 529 i2c1: i2c@ff500000 { 530 compatible = "rockchip,rk3399-i2c"; 531 reg = <0x0 0xff500000 0x0 0x1000>; 532 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 533 clock-names = "i2c", "pclk"; 534 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&i2c1_xfer>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 status = "disabled"; 540 }; 541 542 uart2: serial@ff550000 { 543 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 544 reg = <0x0 0xff550000 0x0 0x100>; 545 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 547 clock-names = "baudclk", "apb_pclk"; 548 reg-shift = <2>; 549 reg-io-width = <4>; 550 dmas = <&dmac 4>, <&dmac 5>; 551 pinctrl-names = "default"; 552 pinctrl-0 = <&uart2m0_xfer>; 553 status = "disabled"; 554 }; 555 556 rktimer: rktimer@ff700000 { 557 compatible = "rockchip,rk3288-timer"; 558 reg = <0x0 0xff700000 0x0 0x1000>; 559 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 561 clock-names = "pclk", "timer"; 562 }; 563 564 npu: npu@ffbc0000 { 565 compatible = "rockchip,npu"; 566 reg = <0x0 0xffbc0000 0x0 0x1000>; 567 clocks = <&cru SCLK_NPU>, <&cru ACLK_NPU>, <&cru HCLK_NPU>; 568 clock-names = "sclk_npu", "aclk_npu", "hclk_npu"; 569 assigned-clocks = <&cru SCLK_NPU>; 570 assigned-clock-rates = <800000000>; 571 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 572 power-domains = <&power RK1808_VD_NPU>; 573 operating-points-v2 = <&npu_opp_table>; 574 #cooling-cells = <2>; 575 status = "disabled"; 576 577 npu_power_model: power-model { 578 compatible = "simple-power-model"; 579 ref-leakage = <31>; 580 static-coefficient = <100000>; 581 dynamic-coefficient = <3080>; 582 ts = <88610 303120 (-5000) 100>; 583 thermal-zone = "soc-thermal"; 584 }; 585 }; 586 587 npu_opp_table: npu-opp-table { 588 compatible = "operating-points-v2"; 589 590 rockchip,max-volt = <880000>; 591 rockchip,evb-irdrop = <37500>; 592 593 rockchip,pvtm-voltage-sel = < 594 0 69000 0 595 69001 74000 1 596 74001 99999 2 597 >; 598 rockchip,pvtm-freq = <200000>; 599 rockchip,pvtm-volt = <800000>; 600 rockchip,pvtm-ch = <0 0>; 601 rockchip,pvtm-sample-time = <1000>; 602 rockchip,pvtm-number = <10>; 603 rockchip,pvtm-error = <1000>; 604 rockchip,pvtm-ref-temp = <25>; 605 rockchip,pvtm-temp-prop = <(-20) (-26)>; 606 rockchip,thermal-zone = "soc-thermal"; 607 608 opp-200000000 { 609 opp-hz = /bits/ 64 <200000000>; 610 opp-microvolt = <750000 750000 880000>; 611 }; 612 opp-297000000 { 613 opp-hz = /bits/ 64 <297000000>; 614 opp-microvolt = <750000 750000 880000>; 615 }; 616 opp-400000000 { 617 opp-hz = /bits/ 64 <400000000>; 618 opp-microvolt = <750000 750000 880000>; 619 }; 620 opp-594000000 { 621 opp-hz = /bits/ 64 <594000000>; 622 opp-microvolt = <750000 750000 880000>; 623 }; 624 opp-792000000 { 625 opp-hz = /bits/ 64 <792000000>; 626 opp-microvolt = <850000 850000 880000>; 627 opp-microvolt-L0 = <850000 850000 880000>; 628 opp-microvolt-L1 = <825000 825000 880000>; 629 opp-microvolt-L2 = <800000 800000 880000>; 630 }; 631 }; 632 633 pinctrl: pinctrl { 634 compatible = "rockchip,rk1808-pinctrl"; 635 rockchip,grf = <&grf>; 636 rockchip,pmu = <&pmugrf>; 637 #address-cells = <2>; 638 #size-cells = <2>; 639 ranges; 640 641 gpio0: gpio0@ff4c0000 { 642 compatible = "rockchip,gpio-bank"; 643 reg = <0x0 0xff4c0000 0x0 0x100>; 644 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&cru PCLK_GPIO0_PMU>, <&cru DBCLK_PMU_GPIO0>; 646 gpio-controller; 647 #gpio-cells = <2>; 648 649 interrupt-controller; 650 #interrupt-cells = <2>; 651 }; 652 653 gpio1: gpio1@ff690000 { 654 compatible = "rockchip,gpio-bank"; 655 reg = <0x0 0xff690000 0x0 0x100>; 656 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 658 gpio-controller; 659 #gpio-cells = <2>; 660 661 interrupt-controller; 662 #interrupt-cells = <2>; 663 }; 664 665 gpio2: gpio2@ff6a0000 { 666 compatible = "rockchip,gpio-bank"; 667 reg = <0x0 0xff6a0000 0x0 0x100>; 668 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 670 gpio-controller; 671 #gpio-cells = <2>; 672 673 interrupt-controller; 674 #interrupt-cells = <2>; 675 }; 676 677 gpio3: gpio3@ff6b0000 { 678 compatible = "rockchip,gpio-bank"; 679 reg = <0x0 0xff6b0000 0x0 0x100>; 680 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 682 gpio-controller; 683 #gpio-cells = <2>; 684 685 interrupt-controller; 686 #interrupt-cells = <2>; 687 }; 688 689 gpio4: gpio4@ff6c0000 { 690 compatible = "rockchip,gpio-bank"; 691 reg = <0x0 0xff6c0000 0x0 0x100>; 692 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 694 gpio-controller; 695 #gpio-cells = <2>; 696 697 interrupt-controller; 698 #interrupt-cells = <2>; 699 }; 700 701 pcfg_pull_down: pcfg-pull-down { 702 bias-pull-down; 703 }; 704 705 pcfg_pull_none: pcfg-pull-none { 706 bias-disable; 707 }; 708 709 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 710 bias-pull-up; 711 drive-strength = <2>; 712 }; 713 714 pcfg_pull_none_smt: pcfg-pull-none-smt { 715 bias-disable; 716 input-schmitt-enable; 717 }; 718 719 pcfg_pull_none_2ma_smt: pcfg-pull-none-2ma-smt { 720 bias-disable; 721 drive-strength = <2>; 722 input-schmitt-enable; 723 }; 724 725 pcfg_output_high: pcfg-output-high { 726 output-high; 727 }; 728 729 pcfg_input_smt: pcfg-input-smt { 730 input-enable; 731 input-schmitt-enable; 732 }; 733 734 i2c0 { 735 i2c0_xfer: i2c0-xfer { 736 rockchip,pins = 737 /* i2c0_sda */ 738 <0 RK_PB1 1 &pcfg_pull_none_2ma_smt>, 739 /* i2c0_scl */ 740 <0 RK_PB0 1 &pcfg_pull_none_2ma_smt>; 741 }; 742 }; 743 744 i2c1 { 745 i2c1_xfer: i2c1-xfer { 746 rockchip,pins = 747 /* i2c1_sda */ 748 <0 RK_PC1 1 &pcfg_pull_none_2ma_smt>, 749 /* i2c1_scl */ 750 <0 RK_PC0 1 &pcfg_pull_none_2ma_smt>; 751 }; 752 }; 753 754 pciusb { 755 pciusb_pins: pciusb-pins { 756 rockchip,pins = 757 /* pciusb_debug0 */ 758 <4 RK_PB4 3 &pcfg_pull_none>, 759 /* pciusb_debug1 */ 760 <4 RK_PB5 3 &pcfg_pull_none>, 761 /* pciusb_debug2 */ 762 <4 RK_PB6 3 &pcfg_pull_none>, 763 /* pciusb_debug3 */ 764 <4 RK_PB7 3 &pcfg_pull_none>, 765 /* pciusb_debug4 */ 766 <4 RK_PC0 3 &pcfg_pull_none>, 767 /* pciusb_debug5 */ 768 <4 RK_PC1 3 &pcfg_pull_none>, 769 /* pciusb_debug6 */ 770 <4 RK_PC2 3 &pcfg_pull_none>, 771 /* pciusb_debug7 */ 772 <4 RK_PC3 3 &pcfg_pull_none>; 773 }; 774 }; 775 776 uart2 { 777 uart2m0_xfer: uart2m0-xfer { 778 rockchip,pins = 779 /* uart2_rxm0 */ 780 <4 RK_PA3 2 &pcfg_pull_up_2ma>, 781 /* uart2_txm0 */ 782 <4 RK_PA2 2 &pcfg_pull_up_2ma>; 783 }; 784 785 uart2m1_xfer: uart2m1-xfer { 786 rockchip,pins = 787 /* uart2_rxm1 */ 788 <2 RK_PD1 2 &pcfg_pull_up_2ma>, 789 /* uart2_txm1 */ 790 <2 RK_PD0 2 &pcfg_pull_up_2ma>; 791 }; 792 793 uart2m2_xfer: uart2m2-xfer { 794 rockchip,pins = 795 /* uart2_rxm2 */ 796 <3 RK_PA4 2 &pcfg_pull_up_2ma>, 797 /* uart2_txm2 */ 798 <3 RK_PA3 2 &pcfg_pull_up_2ma>; 799 }; 800 }; 801 802 tsadc { 803 tsadc_otp_gpio: tsadc-otp-gpio { 804 rockchip,pins = 805 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 806 }; 807 808 tsadc_otp_out: tsadc-otp-out { 809 rockchip,pins = 810 <0 RK_PA6 2 &pcfg_pull_none>; 811 }; 812 }; 813 814 xin32k { 815 clkin_32k: clkin-32k { 816 rockchip,pins = 817 <0 RK_PC2 1 &pcfg_input_smt>; 818 }; 819 820 clkout_32k: clkout-32k { 821 rockchip,pins = 822 <0 RK_PC2 1 &pcfg_output_high>; 823 }; 824 }; 825 }; 826}; 827