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Searched refs:TSP_PVR2_STR2MIU_RST_WADR (Results 1 – 25 of 29) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DhalTSP.c3629 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Exit()
3630 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Exit()
3655 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Start()
3656 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Start()
H A DregTSP.h368 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/
H A DregTSP.h462 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DhalTSP.c4679 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Exit()
4680 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Exit()
4728 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Start()
4729 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Start()
H A DregTSP.h403 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/
H A DregTSP.h463 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010 macro
H A DhalTSP.c1730 u32flag = TSP_PVR2_STR2MIU_RST_WADR; in HAL_TSP_PVR_WaitFlush()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DhalTSP.c4865 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Exit()
4866 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Exit()
4909 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Start()
4910 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Start()
H A DregTSP.h435 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DhalTSP.c5190 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Exit()
5191 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Exit()
5239 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Start()
5240 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR); in HAL_PVR_Start()
H A DregTSP.h439 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DregTSP.h465 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010UL macro
H A DhalTSP.c1786 u32flag = TSP_PVR2_STR2MIU_RST_WADR; in HAL_TSP_PVR_WaitFlush()
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DregTSP.h456 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010UL macro
H A DhalTSP.c1764 u32flag = TSP_PVR2_STR2MIU_RST_WADR; in HAL_TSP_PVR_WaitFlush()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DregTSP.h478 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010UL macro
H A DhalTSP.c1732 u32flag = TSP_PVR2_STR2MIU_RST_WADR; in HAL_TSP_PVR_WaitFlush()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DregTSP.h480 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010UL macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DregTSP.h480 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010UL macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DregTSP.h487 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010UL macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DregTSP.h487 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010UL macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h405 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregTSP.h437 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregTSP.h435 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010 macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregTSP.h435 #define TSP_PVR2_STR2MIU_RST_WADR 0x00000010 macro

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