| /utopia/UTPA2-700.0.x/modules/dmx/hal/messi/tsp/ |
| H A D | regTSP.h | 588 #define TSP_HW_CFG4_PVR_PAUSE 0x00000040UL macro
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/mainz/tsp/ |
| H A D | regTSP.h | 588 #define TSP_HW_CFG4_PVR_PAUSE 0x00000040UL macro
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/mooney/tsp/ |
| H A D | regTSP.h | 582 #define TSP_HW_CFG4_PVR_PAUSE 0x00000040UL macro
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/ |
| H A D | regTSP.h | 683 #define TSP_HW_CFG4_PVR_PAUSE 0x0040 macro
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/ |
| H A D | regTSP.h | 691 #define TSP_HW_CFG4_PVR_PAUSE 0x00000040 macro
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/ |
| H A D | regTSP.h | 691 #define TSP_HW_CFG4_PVR_PAUSE 0x00000040UL macro
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/ |
| H A D | regTSP.h | 680 #define TSP_HW_CFG4_PVR_PAUSE 0x00000040UL macro
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/ |
| H A D | regTSP.h | 711 #define TSP_HW_CFG4_PVR_PAUSE 0x00000040UL macro
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/ |
| H A D | regTSP.h | 716 #define TSP_HW_CFG4_PVR_PAUSE 0x00000040UL macro
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/ |
| H A D | regTSP.h | 716 #define TSP_HW_CFG4_PVR_PAUSE 0x00000040UL macro
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/ |
| H A D | regTSP.h | 723 #define TSP_HW_CFG4_PVR_PAUSE 0x00000040UL macro
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/ |
| H A D | regTSP.h | 723 #define TSP_HW_CFG4_PVR_PAUSE 0x00000040UL macro
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/ |
| H A D | regTSP.h | 588 #define TSP_HW_CFG4_PVR_PAUSE 0x0040 macro
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| H A D | halTSP.c | 3688 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE); in HAL_PVR_Pause()
3702 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE); in HAL_PVR_Pause()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/ |
| H A D | regTSP.h | 624 #define TSP_HW_CFG4_PVR_PAUSE 0x0040 macro
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| H A D | halTSP.c | 4793 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE); in HAL_PVR_Pause()
4813 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE); in HAL_PVR_Pause()
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/ |
| H A D | regTSP.h | 626 #define TSP_HW_CFG4_PVR_PAUSE 0x0040 macro
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/ |
| H A D | regTSP.h | 664 #define TSP_HW_CFG4_PVR_PAUSE 0x0040 macro
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/ |
| H A D | regTSP.h | 656 #define TSP_HW_CFG4_PVR_PAUSE 0x0040 macro
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/ |
| H A D | regTSP.h | 656 #define TSP_HW_CFG4_PVR_PAUSE 0x0040 macro
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/ |
| H A D | regTSP.h | 666 #define TSP_HW_CFG4_PVR_PAUSE 0x0040 macro
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| H A D | halTSP.c | 5303 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE); in HAL_PVR_Pause()
5323 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE); in HAL_PVR_Pause()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/ |
| H A D | regTSP.h | 656 #define TSP_HW_CFG4_PVR_PAUSE 0x0040 macro
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| H A D | halTSP.c | 4966 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE); in HAL_PVR_Pause()
4986 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE); in HAL_PVR_Pause()
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