| /utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/ |
| H A D | regTSP.h | 494 … REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14_0x15 member
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/ |
| H A D | regTSP.h | 494 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14 member
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| H A D | halTSP.c | 1706 u32value = _HAL_REG32_R(&_TspCtrl[0].Str2mi_mid1_wptr_pvr2); in HAL_TSP_PVR_GetBufWrite()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/ |
| H A D | regTSP.h | 497 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14 member
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| H A D | halTSP.c | 1758 u32value = _HAL_REG32_R(&_TspCtrl[0].Str2mi_mid1_wptr_pvr2); in HAL_TSP_PVR_GetBufWrite()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/ |
| H A D | regTSP.h | 489 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14 member
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| H A D | halTSP.c | 1736 u32value = _HAL_REG32_R(&_TspCtrl[0].Str2mi_mid1_wptr_pvr2); in HAL_TSP_PVR_GetBufWrite()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/ |
| H A D | halTSP.c | 3789 … REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (u32StartAddr0>>MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
3841 REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
3882 return (REG32_R(&_RegCtrl->Str2mi_mid1_wptr_pvr2) << MIU_BUS); in HAL_PVR_GetWritePtr()
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| H A D | regTSP.h | 400 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14 member
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/ |
| H A D | regTSP.h | 512 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14 member
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| H A D | halTSP.c | 1704 u32value = _HAL_REG32_R(&_TspCtrl[0].Str2mi_mid1_wptr_pvr2); in HAL_TSP_PVR_GetBufWrite()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/ |
| H A D | regTSP.h | 514 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14 member
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/ |
| H A D | regTSP.h | 514 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14 member
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/ |
| H A D | regTSP.h | 521 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14 member
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/ |
| H A D | regTSP.h | 521 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14 member
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/ |
| H A D | regTSP.h | 435 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14 member
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| H A D | halTSP.c | 4934 …REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MAS… in HAL_PVR_SetBuf()
5057 REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
5134 WritePtr = REG32_R(&_RegCtrl->Str2mi_mid1_wptr_pvr2) << MIU_BUS; in HAL_PVR_GetWritePtr()
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/ |
| H A D | regTSP.h | 437 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14 member
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/ |
| H A D | regTSP.h | 469 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14 member
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/ |
| H A D | regTSP.h | 467 … REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14_0x15 member
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/ |
| H A D | regTSP.h | 467 … REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14_0x15 member
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/ |
| H A D | regTSP.h | 471 REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14 member
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| H A D | halTSP.c | 5444 …REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MAS… in HAL_PVR_SetBuf()
5568 REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
5645 WritePtr = REG32_R(&_RegCtrl->Str2mi_mid1_wptr_pvr2) << MIU_BUS; in HAL_PVR_GetWritePtr()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/ |
| H A D | halTSP.c | 5107 …REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MAS… in HAL_PVR_SetBuf()
5210 REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_MidAddr()
5279 return (REG32_R(&_RegCtrl->Str2mi_mid1_wptr_pvr2) << MIU_BUS); in HAL_PVR_GetWritePtr()
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| H A D | regTSP.h | 467 … REG32 Str2mi_mid1_wptr_pvr2; // 0xbf802a50 0x14_0x15 member
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