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Searched refs:MIU0_REG_SEL4 (Results 1 – 25 of 41) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DhalHVD_EX.c235 #define HVD_MVD_RW_RTO_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(9)) == 0) && ((_HVD…
237 #define HVD_HVD_RW_MIF0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0) && ((_HVD…
238 #define HVD_HVD_RW_MIF1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(5)) == 0) && ((_HVD…
239 #define HVD_HVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(11)) == 0) && ((_HVD…
242 #define HVD_MVD_RW_RTO_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(9)) == BIT(9)) && …
244 #define HVD_HVD_RW_MIF0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == BIT(4)) && …
245 #define HVD_HVD_RW_MIF1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(5)) == BIT(5)) && …
246 #define HVD_HVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(11)) == BIT(11)) && …
249 #define HVD_MVD_RW_RTO_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(9)) == 0) && ((_HVD…
251 #define HVD_HVD_RW_MIF0_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0) && ((_HVD…
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DhalHVD_EX.c239 #define HVD_MVD_RW_1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0) && ((_HVD_…
241 #define HVD_HVD_RW_MIF0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0) && ((_HVD_…
242 #define HVD_HVD_RW_MIF1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0) && ((_HVD_…
243 #define HVD_HVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == 0) && ((_HVD_…
246 #define HVD_MVD_RW_1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == BIT(6)) && ((…
248 #define HVD_HVD_RW_MIF0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == BIT(2)) && ((…
249 #define HVD_HVD_RW_MIF1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == BIT(3)) && ((…
250 #define HVD_HVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == BIT(0)) && ((…
253 #define HVD_MVD_RW_1_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0) && ((_HVD_…
255 #define HVD_HVD_RW_MIF0_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0) && ((_HVD_…
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DhalHVD_EX.c225 #define HVD_MVD_RW_1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0) && ((_HVD_…
227 #define HVD_HVD_RW_MIF0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0) && ((_HVD_…
228 #define HVD_HVD_RW_MIF1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0) && ((_HVD_…
229 #define HVD_HVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == 0) && ((_HVD_…
232 #define HVD_MVD_RW_1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == BIT(6)) && ((…
234 #define HVD_HVD_RW_MIF0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == BIT(2)) && ((…
235 #define HVD_HVD_RW_MIF1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == BIT(3)) && ((…
236 #define HVD_HVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == BIT(0)) && ((…
239 #define HVD_MVD_RW_1_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0) && ((_HVD_…
241 #define HVD_HVD_RW_MIF0_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0) && ((_HVD_…
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DhalHVD_EX.c240 #define HVD_MVD_RW_1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0) && ((_HVD_…
242 #define HVD_HVD_RW_MIF0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0) && ((_HVD_…
243 #define HVD_HVD_RW_MIF1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0) && ((_HVD_…
244 #define HVD_HVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == 0) && ((_HVD_…
247 #define HVD_MVD_RW_1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == BIT(6)) && ((…
249 #define HVD_HVD_RW_MIF0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == BIT(2)) && ((…
250 #define HVD_HVD_RW_MIF1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == BIT(3)) && ((…
251 #define HVD_HVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == BIT(0)) && ((…
254 #define HVD_MVD_RW_1_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0) && ((_HVD_…
256 #define HVD_HVD_RW_MIF0_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0) && ((_HVD_…
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DhalHVD_EX.c239 #define HVD_MVD_RW_1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0) && ((_HVD_…
241 #define HVD_HVD_RW_MIF0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0) && ((_HVD_…
242 #define HVD_HVD_RW_MIF1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0) && ((_HVD_…
243 #define HVD_HVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == 0) && ((_HVD_…
246 #define HVD_MVD_RW_1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == BIT(6)) && ((…
248 #define HVD_HVD_RW_MIF0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == BIT(2)) && ((…
249 #define HVD_HVD_RW_MIF1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == BIT(3)) && ((…
250 #define HVD_HVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == BIT(0)) && ((…
253 #define HVD_MVD_RW_1_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0) && ((_HVD_…
255 #define HVD_HVD_RW_MIF0_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0) && ((_HVD_…
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DhalHVD_EX.c232 #define HVD_MVD_RW_1_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0)
234 #define HVD_HVD_RW_MIF0_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0)
235 #define HVD_HVD_RW_MIF1_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0)
236 #define HVD_HVD_BBU_R_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == 0)
239 #define HVD_MVD_RW_1_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == BIT(6))
241 #define HVD_HVD_RW_MIF0_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == BIT(2))
242 #define HVD_HVD_RW_MIF1_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == BIT(3))
243 #define HVD_HVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == BIT(0))
251 #define HVD_EVD_RW_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0)
252 #define HVD_EVD_BBU_R_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/hvd_v3/
H A DhalHVD_EX.c233 #define HVD_HVD_RW_MIF0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0))
234 #define HVD_HVD_RW_MIF1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(5)) == 0))
235 #define HVD_HVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(11)) == 0))
239 #define HVD_HVD_RW_MIF0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == BIT(4)))
240 #define HVD_HVD_RW_MIF1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(5)) == BIT(5)))
241 #define HVD_HVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(11)) == BIT(11)))
257 #define HVD_EVD_RW1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0))
258 #define HVD_EVD_RW2_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(1)) == 0))
259 #define HVD_EVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(10)) == 0))
261 #define HVD_EVD_RW1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == BIT(7)))
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/hvd_v3/
H A DhalHVD_EX.c233 #define HVD_HVD_RW_MIF0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0))
234 #define HVD_HVD_RW_MIF1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(5)) == 0))
235 #define HVD_HVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(11)) == 0))
239 #define HVD_HVD_RW_MIF0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == BIT(4)))
240 #define HVD_HVD_RW_MIF1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(5)) == BIT(5)))
241 #define HVD_HVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(11)) == BIT(11)))
257 #define HVD_EVD_RW1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0))
258 #define HVD_EVD_RW2_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(1)) == 0))
259 #define HVD_EVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(10)) == 0))
261 #define HVD_EVD_RW1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == BIT(7)))
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DhalHVD_EX.c232 #define HVD_MVD_RW_1_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0)
234 #define HVD_HVD_RW_MIF0_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0)
235 #define HVD_HVD_RW_MIF1_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0)
236 #define HVD_HVD_BBU_R_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == 0)
239 #define HVD_MVD_RW_1_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == BIT(6))
241 #define HVD_HVD_RW_MIF0_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == BIT(2))
242 #define HVD_HVD_RW_MIF1_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == BIT(3))
243 #define HVD_HVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == BIT(0))
251 #define HVD_EVD_RW_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0)
252 #define HVD_EVD_BBU_R_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/hvd_v3/
H A DhalHVD_EX.c233 #define HVD_HVD_RW_MIF0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0))
234 #define HVD_HVD_RW_MIF1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(5)) == 0))
235 #define HVD_HVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(11)) == 0))
239 #define HVD_HVD_RW_MIF0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == BIT(4)))
240 #define HVD_HVD_RW_MIF1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(5)) == BIT(5)))
241 #define HVD_HVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(11)) == BIT(11)))
257 #define HVD_EVD_RW1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0))
258 #define HVD_EVD_RW2_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(1)) == 0))
259 #define HVD_EVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(10)) == 0))
261 #define HVD_EVD_RW1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == BIT(7)))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/hvd_v3/
H A DhalHVD_EX.c231 #define HVD_HVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(1)) == BIT(1))
232 #define HVD_HVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == BIT(0))
243 #define HVD_EVD_RW1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0))
244 #define HVD_EVD_RW2_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0))
245 #define HVD_EVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0))
247 #define HVD_EVD_RW1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == BIT(2)))
248 #define HVD_EVD_RW2_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == BIT(4)))
249 #define HVD_EVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == BIT(3)))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/vpu_v3/
H A DregVPU_EX.h410 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/
H A DregVPU_EX.h429 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/
H A DregVPU_EX.h437 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/
H A DregVPU_EX.h437 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A DregVPU_EX.h437 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/vpu_v3/
H A DregVPU_EX.h446 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A DregVPU_EX.h457 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/vpu_v3/
H A DregVPU_EX.h446 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A DregVPU_EX.h457 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/vpu_v3/
H A DregVPU_EX.h446 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/vpu_lite/
H A DregVPU_EX.h455 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/vpu_v3/
H A DregVPU_EX.h458 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/vpu_v3/
H A DregVPU_EX.h458 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/vpu_v3/
H A DregVPU_EX.h458 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1)) macro

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