Home
last modified time | relevance | path

Searched refs:MIU0_REG_RQ4_MASK (Results 1 – 25 of 40) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DhalHVD_EX.c213 #define _MaskMiuReq_MVD_RW_RTO( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(1))
215 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(4))
216 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(5))
217 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(3))
257 #define _MaskMiuReq_EVD_RW1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
258 #define _MaskMiuReq_EVD_RW2( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(1))
259 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(2))
260 #define _MaskMiuReq_EVD_LITE_RW1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
261 #define _MaskMiuReq_EVD_LITE_RW2( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
262 #define _MaskMiuReq_EVD_LITE_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DhalHVD_EX.c217 #define _MaskMiuReq_MVD_RW_1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
219 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
220 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
221 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
246 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(4))
247 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(4))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DhalHVD_EX.c217 #define _MaskMiuReq_MVD_RW_1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
219 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
220 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
221 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
261 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
262 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DhalHVD_EX.c203 #define _MaskMiuReq_MVD_RW_1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
205 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
206 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
207 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
247 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
248 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/hvd_v3/
H A DhalHVD_EX.c219 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(4))
220 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(5))
221 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(3))
246 #define _MaskMiuReq_EVD_RW1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
247 #define _MaskMiuReq_EVD_RW2( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(1))
248 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(2))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DhalHVD_EX.c218 #define _MaskMiuReq_MVD_RW_1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
220 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
221 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
222 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
262 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
263 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/hvd_v3/
H A DhalHVD_EX.c219 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(4))
220 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(5))
221 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(3))
246 #define _MaskMiuReq_EVD_RW1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
247 #define _MaskMiuReq_EVD_RW2( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(1))
248 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(2))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DhalHVD_EX.c217 #define _MaskMiuReq_MVD_RW_1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
219 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
220 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
221 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
246 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(4))
247 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(4))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/hvd_v3/
H A DhalHVD_EX.c219 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(4))
220 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(5))
221 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(3))
246 #define _MaskMiuReq_EVD_RW1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
247 #define _MaskMiuReq_EVD_RW2( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(1))
248 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(2))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DhalHVD_EX.c217 #define _MaskMiuReq_MVD_RW_1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
219 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
220 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
221 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
261 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
262 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/vpu_v3/
H A DregVPU_EX.h396 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/
H A DregVPU_EX.h407 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/
H A DregVPU_EX.h415 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/
H A DregVPU_EX.h415 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A DregVPU_EX.h415 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/vpu_v3/
H A DregVPU_EX.h432 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A DregVPU_EX.h435 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/vpu_v3/
H A DregVPU_EX.h432 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A DregVPU_EX.h435 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/vpu_v3/
H A DregVPU_EX.h432 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/hvd_v3/
H A DhalHVD_EX.c221 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(1))
222 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
235 #define _MaskMiuReq_EVD_RW1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
236 #define _MaskMiuReq_EVD_RW2( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(4))
237 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/vpu_lite/
H A DregVPU_EX.h433 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/vpu_v3/
H A DregVPU_EX.h435 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/vpu_v3/
H A DregVPU_EX.h435 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/vpu_v3/
H A DregVPU_EX.h435 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1)) macro

12