Home
last modified time | relevance | path

Searched refs:FTN_REG_BASE (Results 1 – 25 of 27) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_DVBT.c137 #define FTN_REG_BASE 0x2800UL macro
2657 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT_Show_AGC_Info()
2658 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT_Show_AGC_Info()
2659 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT_Show_AGC_Info()
2660 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT_Show_AGC_Info()
2666 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT_Show_AGC_Info()
2667 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT_Show_AGC_Info()
2669 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT_Show_AGC_Info()
2671 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT_Show_AGC_Info()
2676 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT_Show_AGC_Info()
[all …]
H A DhalDMD_INTERN_DVBT2.c129 #define FTN_REG_BASE 0x2700 macro
3267 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT2_Show_AGC_Info()
3268 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT2_Show_AGC_Info()
3269 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT2_Show_AGC_Info()
3270 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT2_Show_AGC_Info()
3276 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3277 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT2_Show_AGC_Info()
3279 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3281 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3286 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT2_Show_AGC_Info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_DVBT.c136 #define FTN_REG_BASE 0x2700 macro
2612 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT_Show_AGC_Info()
2613 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT_Show_AGC_Info()
2614 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT_Show_AGC_Info()
2615 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT_Show_AGC_Info()
2621 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT_Show_AGC_Info()
2622 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT_Show_AGC_Info()
2624 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT_Show_AGC_Info()
2626 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT_Show_AGC_Info()
2631 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT_Show_AGC_Info()
[all …]
H A DhalDMD_INTERN_DVBT2.c129 #define FTN_REG_BASE 0x2700 macro
2872 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT2_Show_AGC_Info()
2873 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT2_Show_AGC_Info()
2874 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT2_Show_AGC_Info()
2875 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT2_Show_AGC_Info()
2881 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT2_Show_AGC_Info()
2882 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT2_Show_AGC_Info()
2884 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT2_Show_AGC_Info()
2886 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT2_Show_AGC_Info()
2891 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT2_Show_AGC_Info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBT.c136 #define FTN_REG_BASE 0x2800UL macro
2663 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT_Show_AGC_Info()
2664 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT_Show_AGC_Info()
2665 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT_Show_AGC_Info()
2666 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT_Show_AGC_Info()
2672 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT_Show_AGC_Info()
2673 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT_Show_AGC_Info()
2675 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT_Show_AGC_Info()
2677 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT_Show_AGC_Info()
2682 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT_Show_AGC_Info()
[all …]
H A DhalDMD_INTERN_DVBT2.c129 #define FTN_REG_BASE 0x2700 macro
3291 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT2_Show_AGC_Info()
3292 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT2_Show_AGC_Info()
3293 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT2_Show_AGC_Info()
3294 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT2_Show_AGC_Info()
3300 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3301 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT2_Show_AGC_Info()
3303 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3305 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3310 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT2_Show_AGC_Info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/
H A DhalDMD_INTERN_DVBT.c136 #define FTN_REG_BASE 0x2700UL macro
2985 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT_Show_AGC_Info()
2986 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT_Show_AGC_Info()
2987 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT_Show_AGC_Info()
2988 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT_Show_AGC_Info()
2994 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT_Show_AGC_Info()
2995 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT_Show_AGC_Info()
2997 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT_Show_AGC_Info()
2999 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT_Show_AGC_Info()
3004 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT_Show_AGC_Info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_DVBT.c137 #define FTN_REG_BASE 0x2700UL macro
2720 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT_Show_AGC_Info()
2721 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT_Show_AGC_Info()
2722 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT_Show_AGC_Info()
2723 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT_Show_AGC_Info()
2729 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT_Show_AGC_Info()
2730 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT_Show_AGC_Info()
2732 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT_Show_AGC_Info()
2734 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT_Show_AGC_Info()
2739 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT_Show_AGC_Info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBT.c137 #define FTN_REG_BASE 0x2700UL macro
2820 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT_Show_AGC_Info()
2821 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT_Show_AGC_Info()
2822 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT_Show_AGC_Info()
2823 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT_Show_AGC_Info()
2829 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT_Show_AGC_Info()
2830 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT_Show_AGC_Info()
2832 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT_Show_AGC_Info()
2834 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT_Show_AGC_Info()
2839 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT_Show_AGC_Info()
[all …]
H A DhalDMD_INTERN_DVBT2.c129 #define FTN_REG_BASE 0x2700 macro
3583 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT2_Show_AGC_Info()
3584 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT2_Show_AGC_Info()
3585 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT2_Show_AGC_Info()
3586 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT2_Show_AGC_Info()
3592 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3593 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT2_Show_AGC_Info()
3595 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3597 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3602 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT2_Show_AGC_Info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_DVBT.c136 #define FTN_REG_BASE 0x2700UL macro
3007 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT_Show_AGC_Info()
3008 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT_Show_AGC_Info()
3009 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT_Show_AGC_Info()
3010 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT_Show_AGC_Info()
3016 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT_Show_AGC_Info()
3017 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT_Show_AGC_Info()
3019 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT_Show_AGC_Info()
3021 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT_Show_AGC_Info()
3026 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT_Show_AGC_Info()
[all …]
H A DhalDMD_INTERN_DVBT2.c129 #define FTN_REG_BASE 0x2700 macro
3153 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT2_Show_AGC_Info()
3154 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT2_Show_AGC_Info()
3155 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT2_Show_AGC_Info()
3156 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT2_Show_AGC_Info()
3162 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3163 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT2_Show_AGC_Info()
3165 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3167 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3172 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT2_Show_AGC_Info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DVBT.c137 #define FTN_REG_BASE 0x2700UL macro
2720 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT_Show_AGC_Info()
2721 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT_Show_AGC_Info()
2722 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT_Show_AGC_Info()
2723 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT_Show_AGC_Info()
2729 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT_Show_AGC_Info()
2730 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT_Show_AGC_Info()
2732 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT_Show_AGC_Info()
2734 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT_Show_AGC_Info()
2739 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT_Show_AGC_Info()
[all …]
H A DhalDMD_INTERN_DVBT2.c129 #define FTN_REG_BASE 0x2700 macro
3437 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT2_Show_AGC_Info()
3438 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT2_Show_AGC_Info()
3439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT2_Show_AGC_Info()
3440 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT2_Show_AGC_Info()
3446 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3447 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT2_Show_AGC_Info()
3449 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3451 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3456 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT2_Show_AGC_Info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_DVBT.c137 #define FTN_REG_BASE 0x2700UL macro
2720 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT_Show_AGC_Info()
2721 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT_Show_AGC_Info()
2722 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT_Show_AGC_Info()
2723 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT_Show_AGC_Info()
2729 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT_Show_AGC_Info()
2730 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT_Show_AGC_Info()
2732 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT_Show_AGC_Info()
2734 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT_Show_AGC_Info()
2739 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT_Show_AGC_Info()
[all …]
H A DhalDMD_INTERN_DVBT2.c129 #define FTN_REG_BASE 0x2700 macro
3437 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT2_Show_AGC_Info()
3438 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT2_Show_AGC_Info()
3439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT2_Show_AGC_Info()
3440 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT2_Show_AGC_Info()
3446 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3447 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT2_Show_AGC_Info()
3449 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3451 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3456 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT2_Show_AGC_Info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/
H A DhalDMD_INTERN_DVBT.c137 #define FTN_REG_BASE 0x2700UL macro
2967 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT_Show_AGC_Info()
2968 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT_Show_AGC_Info()
2969 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT_Show_AGC_Info()
2970 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT_Show_AGC_Info()
2976 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT_Show_AGC_Info()
2977 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT_Show_AGC_Info()
2979 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT_Show_AGC_Info()
2981 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT_Show_AGC_Info()
2986 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT_Show_AGC_Info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_DVBT.c137 #define FTN_REG_BASE 0x2700UL macro
2720 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT_Show_AGC_Info()
2721 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT_Show_AGC_Info()
2722 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT_Show_AGC_Info()
2723 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT_Show_AGC_Info()
2729 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT_Show_AGC_Info()
2730 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT_Show_AGC_Info()
2732 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT_Show_AGC_Info()
2734 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT_Show_AGC_Info()
2739 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT_Show_AGC_Info()
[all …]
H A DhalDMD_INTERN_DVBT2.c129 #define FTN_REG_BASE 0x2700 macro
3437 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT2_Show_AGC_Info()
3438 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT2_Show_AGC_Info()
3439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT2_Show_AGC_Info()
3440 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT2_Show_AGC_Info()
3446 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3447 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT2_Show_AGC_Info()
3449 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3451 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3456 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT2_Show_AGC_Info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_DVBT.c137 #define FTN_REG_BASE 0x2700UL macro
2720 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT_Show_AGC_Info()
2721 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT_Show_AGC_Info()
2722 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT_Show_AGC_Info()
2723 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT_Show_AGC_Info()
2729 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT_Show_AGC_Info()
2730 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT_Show_AGC_Info()
2732 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT_Show_AGC_Info()
2734 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT_Show_AGC_Info()
2739 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT_Show_AGC_Info()
[all …]
H A DhalDMD_INTERN_DVBT2.c129 #define FTN_REG_BASE 0x2700 macro
3437 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT2_Show_AGC_Info()
3438 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT2_Show_AGC_Info()
3439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT2_Show_AGC_Info()
3440 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT2_Show_AGC_Info()
3446 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3447 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT2_Show_AGC_Info()
3449 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3451 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3456 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT2_Show_AGC_Info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_DVBT.c137 #define FTN_REG_BASE 0x2700UL macro
2720 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT_Show_AGC_Info()
2721 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT_Show_AGC_Info()
2722 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT_Show_AGC_Info()
2723 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT_Show_AGC_Info()
2729 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT_Show_AGC_Info()
2730 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT_Show_AGC_Info()
2732 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT_Show_AGC_Info()
2734 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT_Show_AGC_Info()
2739 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT_Show_AGC_Info()
[all …]
H A DhalDMD_INTERN_DVBT2.c129 #define FTN_REG_BASE 0x2700 macro
3437 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT2_Show_AGC_Info()
3438 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT2_Show_AGC_Info()
3439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT2_Show_AGC_Info()
3440 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT2_Show_AGC_Info()
3446 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3447 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT2_Show_AGC_Info()
3449 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3451 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3456 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT2_Show_AGC_Info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBT.c137 #define FTN_REG_BASE 0x2700UL macro
2820 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT_Show_AGC_Info()
2821 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT_Show_AGC_Info()
2822 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT_Show_AGC_Info()
2823 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT_Show_AGC_Info()
2829 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT_Show_AGC_Info()
2830 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT_Show_AGC_Info()
2832 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT_Show_AGC_Info()
2834 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT_Show_AGC_Info()
2839 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT_Show_AGC_Info()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mainz/demod/
H A DhalDMD_INTERN_DVBT.c137 #define FTN_REG_BASE 0x2700UL macro
2994 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k); in INTERN_DVBT_Show_AGC_Info()
2995 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref); in INTERN_DVBT_Show_AGC_Info()
2996 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k); in INTERN_DVBT_Show_AGC_Info()
2997 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref); in INTERN_DVBT_Show_AGC_Info()
3003 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp); in INTERN_DVBT_Show_AGC_Info()
3004 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03); in INTERN_DVBT_Show_AGC_Info()
3006 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp); in INTERN_DVBT_Show_AGC_Info()
3008 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp); in INTERN_DVBT_Show_AGC_Info()
3013 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp); in INTERN_DVBT_Show_AGC_Info()
[all …]

12