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Searched refs:FTNEXT_REG_BASE (Results 1 – 25 of 27) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_DVBT.c138 #define FTNEXT_REG_BASE 0x2900UL macro
2661 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT_Show_AGC_Info()
2662 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT_Show_AGC_Info()
2685 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT_Show_AGC_Info()
2686 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT_Show_AGC_Info()
2688 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT_Show_AGC_Info()
2690 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT_Show_AGC_Info()
2704 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT_Show_AGC_Info()
H A DhalDMD_INTERN_DVBT2.c130 #define FTNEXT_REG_BASE 0x2800 macro
3271 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT2_Show_AGC_Info()
3272 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT2_Show_AGC_Info()
3295 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3296 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT2_Show_AGC_Info()
3298 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3300 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3314 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT2_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_DVBT.c137 #define FTNEXT_REG_BASE 0x2800 macro
2616 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT_Show_AGC_Info()
2617 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT_Show_AGC_Info()
2640 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT_Show_AGC_Info()
2641 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT_Show_AGC_Info()
2643 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT_Show_AGC_Info()
2645 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT_Show_AGC_Info()
2659 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT_Show_AGC_Info()
H A DhalDMD_INTERN_DVBT2.c130 #define FTNEXT_REG_BASE 0x2800 macro
2876 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT2_Show_AGC_Info()
2877 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT2_Show_AGC_Info()
2900 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT2_Show_AGC_Info()
2901 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT2_Show_AGC_Info()
2903 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT2_Show_AGC_Info()
2905 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT2_Show_AGC_Info()
2919 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT2_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBT.c137 #define FTNEXT_REG_BASE 0x2900UL macro
2667 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT_Show_AGC_Info()
2668 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT_Show_AGC_Info()
2691 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT_Show_AGC_Info()
2692 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT_Show_AGC_Info()
2694 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT_Show_AGC_Info()
2696 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT_Show_AGC_Info()
2710 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT_Show_AGC_Info()
H A DhalDMD_INTERN_DVBT2.c130 #define FTNEXT_REG_BASE 0x2800 macro
3295 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT2_Show_AGC_Info()
3296 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT2_Show_AGC_Info()
3319 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3320 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT2_Show_AGC_Info()
3322 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3324 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3338 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT2_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/
H A DhalDMD_INTERN_DVBT.c137 #define FTNEXT_REG_BASE 0x2800UL macro
2989 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT_Show_AGC_Info()
2990 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT_Show_AGC_Info()
3013 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT_Show_AGC_Info()
3014 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT_Show_AGC_Info()
3016 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT_Show_AGC_Info()
3018 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT_Show_AGC_Info()
3032 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_DVBT.c138 #define FTNEXT_REG_BASE 0x2800UL macro
2724 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT_Show_AGC_Info()
2725 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT_Show_AGC_Info()
2748 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT_Show_AGC_Info()
2749 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT_Show_AGC_Info()
2751 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT_Show_AGC_Info()
2753 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT_Show_AGC_Info()
2767 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBT.c138 #define FTNEXT_REG_BASE 0x2800UL macro
2824 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT_Show_AGC_Info()
2825 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT_Show_AGC_Info()
2848 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT_Show_AGC_Info()
2849 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT_Show_AGC_Info()
2851 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT_Show_AGC_Info()
2853 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT_Show_AGC_Info()
2867 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT_Show_AGC_Info()
H A DhalDMD_INTERN_DVBT2.c130 #define FTNEXT_REG_BASE 0x2800 macro
3587 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT2_Show_AGC_Info()
3588 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT2_Show_AGC_Info()
3611 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3612 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT2_Show_AGC_Info()
3614 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3616 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3630 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT2_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_DVBT.c137 #define FTNEXT_REG_BASE 0x2800UL macro
3011 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT_Show_AGC_Info()
3012 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT_Show_AGC_Info()
3035 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT_Show_AGC_Info()
3036 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT_Show_AGC_Info()
3038 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT_Show_AGC_Info()
3040 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT_Show_AGC_Info()
3054 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT_Show_AGC_Info()
H A DhalDMD_INTERN_DVBT2.c130 #define FTNEXT_REG_BASE 0x2800 macro
3157 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT2_Show_AGC_Info()
3158 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT2_Show_AGC_Info()
3181 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3182 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT2_Show_AGC_Info()
3184 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3186 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3200 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT2_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DVBT.c138 #define FTNEXT_REG_BASE 0x2800UL macro
2724 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT_Show_AGC_Info()
2725 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT_Show_AGC_Info()
2748 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT_Show_AGC_Info()
2749 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT_Show_AGC_Info()
2751 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT_Show_AGC_Info()
2753 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT_Show_AGC_Info()
2767 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT_Show_AGC_Info()
H A DhalDMD_INTERN_DVBT2.c130 #define FTNEXT_REG_BASE 0x2800 macro
3441 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT2_Show_AGC_Info()
3442 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT2_Show_AGC_Info()
3465 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3466 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT2_Show_AGC_Info()
3468 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3470 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3484 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT2_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_DVBT.c138 #define FTNEXT_REG_BASE 0x2800UL macro
2724 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT_Show_AGC_Info()
2725 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT_Show_AGC_Info()
2748 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT_Show_AGC_Info()
2749 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT_Show_AGC_Info()
2751 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT_Show_AGC_Info()
2753 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT_Show_AGC_Info()
2767 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT_Show_AGC_Info()
H A DhalDMD_INTERN_DVBT2.c130 #define FTNEXT_REG_BASE 0x2800 macro
3441 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT2_Show_AGC_Info()
3442 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT2_Show_AGC_Info()
3465 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3466 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT2_Show_AGC_Info()
3468 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3470 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3484 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT2_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/
H A DhalDMD_INTERN_DVBT.c138 #define FTNEXT_REG_BASE 0x2800UL macro
2971 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT_Show_AGC_Info()
2972 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT_Show_AGC_Info()
2995 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT_Show_AGC_Info()
2996 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT_Show_AGC_Info()
2998 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT_Show_AGC_Info()
3000 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT_Show_AGC_Info()
3014 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_DVBT.c138 #define FTNEXT_REG_BASE 0x2800UL macro
2724 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT_Show_AGC_Info()
2725 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT_Show_AGC_Info()
2748 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT_Show_AGC_Info()
2749 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT_Show_AGC_Info()
2751 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT_Show_AGC_Info()
2753 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT_Show_AGC_Info()
2767 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT_Show_AGC_Info()
H A DhalDMD_INTERN_DVBT2.c130 #define FTNEXT_REG_BASE 0x2800 macro
3441 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT2_Show_AGC_Info()
3442 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT2_Show_AGC_Info()
3465 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3466 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT2_Show_AGC_Info()
3468 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3470 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3484 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT2_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_DVBT.c138 #define FTNEXT_REG_BASE 0x2800UL macro
2724 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT_Show_AGC_Info()
2725 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT_Show_AGC_Info()
2748 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT_Show_AGC_Info()
2749 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT_Show_AGC_Info()
2751 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT_Show_AGC_Info()
2753 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT_Show_AGC_Info()
2767 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT_Show_AGC_Info()
H A DhalDMD_INTERN_DVBT2.c130 #define FTNEXT_REG_BASE 0x2800 macro
3441 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT2_Show_AGC_Info()
3442 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT2_Show_AGC_Info()
3465 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3466 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT2_Show_AGC_Info()
3468 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3470 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3484 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT2_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_DVBT.c138 #define FTNEXT_REG_BASE 0x2800UL macro
2724 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT_Show_AGC_Info()
2725 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT_Show_AGC_Info()
2748 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT_Show_AGC_Info()
2749 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT_Show_AGC_Info()
2751 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT_Show_AGC_Info()
2753 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT_Show_AGC_Info()
2767 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT_Show_AGC_Info()
H A DhalDMD_INTERN_DVBT2.c130 #define FTNEXT_REG_BASE 0x2800 macro
3441 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT2_Show_AGC_Info()
3442 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT2_Show_AGC_Info()
3465 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3466 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT2_Show_AGC_Info()
3468 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3470 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT2_Show_AGC_Info()
3484 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT2_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBT.c138 #define FTNEXT_REG_BASE 0x2800UL macro
2824 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT_Show_AGC_Info()
2825 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT_Show_AGC_Info()
2848 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT_Show_AGC_Info()
2849 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT_Show_AGC_Info()
2851 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT_Show_AGC_Info()
2853 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT_Show_AGC_Info()
2867 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT_Show_AGC_Info()
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mainz/demod/
H A DhalDMD_INTERN_DVBT.c138 #define FTNEXT_REG_BASE 0x2800UL macro
2998 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k); in INTERN_DVBT_Show_AGC_Info()
2999 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref); in INTERN_DVBT_Show_AGC_Info()
3022 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp); in INTERN_DVBT_Show_AGC_Info()
3023 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02); in INTERN_DVBT_Show_AGC_Info()
3025 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp); in INTERN_DVBT_Show_AGC_Info()
3027 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp); in INTERN_DVBT_Show_AGC_Info()
3041 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock); in INTERN_DVBT_Show_AGC_Info()

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