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Searched refs:ADC_CH_I_PGA_GAIN_CTRL (Results 1 – 25 of 27) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_DVBT.c184 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
186 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
H A DhalDMD_INTERN_DVBT2.c180 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
182 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_DVBT.c182 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
184 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
H A DhalDMD_INTERN_DVBT2.c175 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
177 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_DVBT.c183 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
185 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
H A DhalDMD_INTERN_DVBT2.c184 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
186 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/
H A DhalDMD_INTERN_DVBT.c182 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
184 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_DVBT.c185 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
187 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_DVBT.c185 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
187 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
H A DhalDMD_INTERN_DVBT2.c183 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
185 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_DVBT.c184 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
186 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
H A DhalDMD_INTERN_DVBT2.c175 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
177 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_DVBT.c185 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
187 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
H A DhalDMD_INTERN_DVBT2.c175 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
177 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_DVBT.c185 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
187 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
H A DhalDMD_INTERN_DVBT2.c175 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
177 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/
H A DhalDMD_INTERN_DVBT.c183 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
185 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_DVBT.c185 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
187 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
H A DhalDMD_INTERN_DVBT2.c175 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
177 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_DVBT.c185 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
187 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
H A DhalDMD_INTERN_DVBT2.c175 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
177 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_DVBT.c185 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
187 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
H A DhalDMD_INTERN_DVBT2.c175 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
177 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_DVBT.c185 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
187 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro
/utopia/UTPA2-700.0.x/modules/demodulator/hal/mainz/demod/
H A DhalDMD_INTERN_DVBT.c183 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0 macro
185 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0 macro

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