| /rockchip-linux_mpp/mpp/hal/rkdec/h264d/ |
| H A D | hal_h264d_vdpu384a.c | 381 regs->ctrl_regs.reg9.dpb_data_sel = 0; in set_registers()
382 regs->ctrl_regs.reg9.dpb_output_dis = 0; in set_registers()
383 regs->ctrl_regs.reg9.pp_m_output_mode = 0; in set_registers()
389 regs->ctrl_regs.reg9.dpb_data_sel = 1; in set_registers()
390 regs->ctrl_regs.reg9.dpb_output_dis = 1; in set_registers()
391 regs->ctrl_regs.reg9.pp_m_output_mode = 2; in set_registers()
397 regs->ctrl_regs.reg9.dpb_data_sel = 1; in set_registers()
398 regs->ctrl_regs.reg9.dpb_output_dis = 1; in set_registers()
399 regs->ctrl_regs.reg9.pp_m_output_mode = 1; in set_registers()
526 … vdpu384a_setup_down_scale(mframe, p_hal->dev, ®s->ctrl_regs, (void*)®s->h264d_paras); in set_registers()
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| H A D | hal_h264d_vdpu383.c | 445 regs->ctrl_regs.reg9.fbc_e = 1; in set_registers()
449 regs->ctrl_regs.reg9.tile_e = 1; in set_registers()
453 regs->ctrl_regs.reg9.fbc_e = 0; in set_registers()
571 … vdpu383_setup_down_scale(mframe, p_hal->dev, ®s->ctrl_regs, (void*)®s->h264d_paras); in set_registers()
575 … vdpu383_setup_down_scale(mframe, p_hal->dev, ®s->ctrl_regs, (void*)®s->h264d_paras); in set_registers()
579 regs->ctrl_regs.reg9.scale_down_en = 0; in set_registers()
589 Vdpu383CtrlReg *ctrl_regs = ®s->ctrl_regs; in init_ctrl_regs() local
591 ctrl_regs->reg8_dec_mode = 1; //!< h264 in init_ctrl_regs()
592 ctrl_regs->reg9.buf_empty_en = 0; in init_ctrl_regs()
594 ctrl_regs->reg10.strmd_auto_gating_e = 1; in init_ctrl_regs()
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| /rockchip-linux_mpp/mpp/hal/rkdec/avs2d/ |
| H A D | hal_avs2d_vdpu383.c | 238 Vdpu383CtrlReg *ctrl_regs = ®s->ctrl_regs; in init_ctrl_regs() local
240 ctrl_regs->reg8_dec_mode = 3; // AVS2 in init_ctrl_regs()
241 ctrl_regs->reg9.buf_empty_en = 1; in init_ctrl_regs()
243 ctrl_regs->reg10.strmd_auto_gating_e = 1; in init_ctrl_regs()
244 ctrl_regs->reg10.inter_auto_gating_e = 1; in init_ctrl_regs()
245 ctrl_regs->reg10.intra_auto_gating_e = 1; in init_ctrl_regs()
246 ctrl_regs->reg10.transd_auto_gating_e = 1; in init_ctrl_regs()
247 ctrl_regs->reg10.recon_auto_gating_e = 1; in init_ctrl_regs()
248 ctrl_regs->reg10.filterd_auto_gating_e = 1; in init_ctrl_regs()
249 ctrl_regs->reg10.bus_auto_gating_e = 1; in init_ctrl_regs()
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| /rockchip-linux_mpp/mpp/hal/rkdec/ |
| H A D | vdpu383_com.c | 110 void vdpu383_setup_statistic(Vdpu383CtrlReg *ctrl_regs) in vdpu383_setup_statistic() argument
112 ctrl_regs->reg28.axi_perf_work_e = 1; in vdpu383_setup_statistic()
113 ctrl_regs->reg28.axi_cnt_type = 1; in vdpu383_setup_statistic()
114 ctrl_regs->reg28.rd_latency_id = 11; in vdpu383_setup_statistic()
116 ctrl_regs->reg29.addr_align_type = 1; in vdpu383_setup_statistic()
117 ctrl_regs->reg29.ar_cnt_id_type = 0; in vdpu383_setup_statistic()
118 ctrl_regs->reg29.aw_cnt_id_type = 1; in vdpu383_setup_statistic()
119 ctrl_regs->reg29.ar_count_id = 17; in vdpu383_setup_statistic()
120 ctrl_regs->reg29.aw_count_id = 0; in vdpu383_setup_statistic()
121 ctrl_regs->reg29.rd_band_width_mode = 0; in vdpu383_setup_statistic()
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| H A D | vdpu384a_com.c | 122 void vdpu384a_setup_statistic(Vdpu384aCtrlReg *ctrl_regs) in vdpu384a_setup_statistic() argument
124 ctrl_regs->reg28.axi_perf_work_e = 1; in vdpu384a_setup_statistic()
125 ctrl_regs->reg28.axi_cnt_type = 1; in vdpu384a_setup_statistic()
126 ctrl_regs->reg28.rd_latency_id = 11; in vdpu384a_setup_statistic()
128 ctrl_regs->reg29.addr_align_type = 1; in vdpu384a_setup_statistic()
129 ctrl_regs->reg29.ar_cnt_id_type = 0; in vdpu384a_setup_statistic()
130 ctrl_regs->reg29.aw_cnt_id_type = 1; in vdpu384a_setup_statistic()
131 ctrl_regs->reg29.ar_count_id = 17; in vdpu384a_setup_statistic()
132 ctrl_regs->reg29.aw_count_id = 0; in vdpu384a_setup_statistic()
133 ctrl_regs->reg29.rd_band_width_mode = 0; in vdpu384a_setup_statistic()
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| /rockchip-linux_mpp/mpp/hal/rkdec/h265d/ |
| H A D | hal_h265d_vdpu384a.c | 906 hw_regs->ctrl_regs.reg9.dpb_data_sel = 0; in hal_h265d_vdpu384a_gen_regs()
907 hw_regs->ctrl_regs.reg9.dpb_output_dis = 0; in hal_h265d_vdpu384a_gen_regs()
908 hw_regs->ctrl_regs.reg9.pp_m_output_mode = 0; in hal_h265d_vdpu384a_gen_regs()
915 hw_regs->ctrl_regs.reg9.dpb_data_sel = 1; in hal_h265d_vdpu384a_gen_regs()
916 hw_regs->ctrl_regs.reg9.dpb_output_dis = 1; in hal_h265d_vdpu384a_gen_regs()
917 hw_regs->ctrl_regs.reg9.pp_m_output_mode = 2; in hal_h265d_vdpu384a_gen_regs()
931 hw_regs->ctrl_regs.reg9.dpb_data_sel = 1; in hal_h265d_vdpu384a_gen_regs()
932 hw_regs->ctrl_regs.reg9.dpb_output_dis = 1; in hal_h265d_vdpu384a_gen_regs()
933 hw_regs->ctrl_regs.reg9.pp_m_output_mode = 1; in hal_h265d_vdpu384a_gen_regs()
1012 hw_regs->ctrl_regs.reg8_dec_mode = 0; // hevc in hal_h265d_vdpu384a_gen_regs()
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| H A D | hal_h265d_vdpu383.c | 994 hw_regs->ctrl_regs.reg9.fbc_e = 1; in hal_h265d_vdpu383_gen_regs()
999 hw_regs->ctrl_regs.reg9.tile_e = 1; in hal_h265d_vdpu383_gen_regs()
1011 hw_regs->ctrl_regs.reg9.fbc_e = 0; in hal_h265d_vdpu383_gen_regs()
1079 hw_regs->ctrl_regs.reg8_dec_mode = 0; // hevc in hal_h265d_vdpu383_gen_regs()
1080 hw_regs->ctrl_regs.reg9.buf_empty_en = 0; in hal_h265d_vdpu383_gen_regs()
1082 hw_regs->ctrl_regs.reg10.strmd_auto_gating_e = 1; in hal_h265d_vdpu383_gen_regs()
1083 hw_regs->ctrl_regs.reg10.inter_auto_gating_e = 1; in hal_h265d_vdpu383_gen_regs()
1084 hw_regs->ctrl_regs.reg10.intra_auto_gating_e = 1; in hal_h265d_vdpu383_gen_regs()
1085 hw_regs->ctrl_regs.reg10.transd_auto_gating_e = 1; in hal_h265d_vdpu383_gen_regs()
1086 hw_regs->ctrl_regs.reg10.recon_auto_gating_e = 1; in hal_h265d_vdpu383_gen_regs()
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| /rockchip-linux_mpp/mpp/hal/rkdec/vp9d/ |
| H A D | hal_vp9d_vdpu383.c | 861 vp9_hw_regs->ctrl_regs.reg9.fbc_e = 1; in hal_vp9d_vdpu383_gen_regs()
873 vp9_hw_regs->ctrl_regs.reg9.fbc_e = 0; in hal_vp9d_vdpu383_gen_regs()
875 vp9_hw_regs->ctrl_regs.reg9.tile_e = 1; in hal_vp9d_vdpu383_gen_regs()
879 vp9_hw_regs->ctrl_regs.reg9.tile_e = 0; in hal_vp9d_vdpu383_gen_regs()
1020 vp9_hw_regs->ctrl_regs.reg8_dec_mode = 2; //set as vp9 dec in hal_vp9d_vdpu383_gen_regs()
1021 vp9_hw_regs->ctrl_regs.reg9.buf_empty_en = 0; in hal_vp9d_vdpu383_gen_regs()
1023 vp9_hw_regs->ctrl_regs.reg10.strmd_auto_gating_e = 1; in hal_vp9d_vdpu383_gen_regs()
1024 vp9_hw_regs->ctrl_regs.reg10.inter_auto_gating_e = 1; in hal_vp9d_vdpu383_gen_regs()
1025 vp9_hw_regs->ctrl_regs.reg10.intra_auto_gating_e = 1; in hal_vp9d_vdpu383_gen_regs()
1026 vp9_hw_regs->ctrl_regs.reg10.transd_auto_gating_e = 1; in hal_vp9d_vdpu383_gen_regs()
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| /rockchip-linux_mpp/mpp/hal/rkdec/av1d/ |
| H A D | hal_av1d_vdpu383.c | 2232 regs->ctrl_regs.reg8_dec_mode = 4; // av1 in vdpu383_av1d_gen_regs()
2233 regs->ctrl_regs.reg9.fbc_e = 0; in vdpu383_av1d_gen_regs()
2234 regs->ctrl_regs.reg9.buf_empty_en = 0; in vdpu383_av1d_gen_regs()
2236 regs->ctrl_regs.reg10.strmd_auto_gating_e = 1; in vdpu383_av1d_gen_regs()
2237 regs->ctrl_regs.reg10.inter_auto_gating_e = 1; in vdpu383_av1d_gen_regs()
2238 regs->ctrl_regs.reg10.intra_auto_gating_e = 1; in vdpu383_av1d_gen_regs()
2239 regs->ctrl_regs.reg10.transd_auto_gating_e = 1; in vdpu383_av1d_gen_regs()
2240 regs->ctrl_regs.reg10.recon_auto_gating_e = 1; in vdpu383_av1d_gen_regs()
2241 regs->ctrl_regs.reg10.filterd_auto_gating_e = 1; in vdpu383_av1d_gen_regs()
2242 regs->ctrl_regs.reg10.bus_auto_gating_e = 1; in vdpu383_av1d_gen_regs()
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| /rockchip-linux_mpp/mpp/hal/rkdec/inc/ |
| H A D | vdpu383_h264d.h | 167 Vdpu383CtrlReg ctrl_regs; /* 8-30 */ member
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| H A D | vdpu383_avs2d.h | 168 Vdpu383CtrlReg ctrl_regs; /* 8-30 */ member
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| H A D | vdpu383_h265d.h | 166 Vdpu383CtrlReg ctrl_regs; /* 8-30 */ member
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| H A D | vdpu384a_h265d.h | 172 Vdpu384aCtrlReg ctrl_regs; /* 8-30 */ member
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| H A D | vdpu384a_h264d.h | 173 Vdpu384aCtrlReg ctrl_regs; /* 8-30 */ member
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| H A D | vdpu383_vp9d.h | 178 Vdpu383CtrlReg ctrl_regs; /* 8-30 */ member
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| H A D | vdpu383_av1d.h | 262 Vdpu383CtrlReg ctrl_regs; /* 8-30 */ member
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