1 /* SPDX-License-Identifier: Apache-2.0 OR MIT */ 2 /* 3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __VDPU383_AVS2D_H__ 7 #define __VDPU383_AVS2D_H__ 8 9 #include "vdpu383_com.h" 10 11 #define AVS2D_REGISTERS (278) 12 13 typedef struct Vdpu383RegAvs2dParas_t { 14 /* SWREG64_H26X_PARA */ 15 RK_U32 reg64_unused_bits; 16 17 /* SWREG65_STREAM_PARAM_SET */ 18 RK_U32 reg65_strm_start_bit; 19 20 /* SWREG66_STREAM_LEN */ 21 RK_U32 reg66_stream_len; 22 23 /* SWREG67_GLOBAL_LEN */ 24 RK_U32 reg67_global_len; 25 26 /* SWREG68_HOR_STRIDE */ 27 RK_U32 reg68_hor_virstride; 28 29 /* SWREG69_RASTER_UV_HOR_STRIDE */ 30 RK_U32 reg69_raster_uv_hor_virstride; 31 32 /* SWREG70_Y_STRIDE */ 33 RK_U32 reg70_y_virstride; 34 35 /* SWREG71_SCL_Y_HOR_VIRSTRIDE */ 36 RK_U32 reg71_scl_ref_hor_virstride; 37 38 /* SWREG72_SCL_UV_HOR_VIRSTRIDE */ 39 RK_U32 reg72_scl_ref_raster_uv_hor_virstride; 40 41 /* SWREG73_SCL_Y_VIRSTRIDE */ 42 RK_U32 reg73_scl_ref_virstride; 43 44 /* SWREG74_FGS_Y_HOR_VIRSTRIDE */ 45 RK_U32 reg74_fgs_ref_hor_virstride; 46 47 RK_U32 reserve_reg75_79[5]; 48 49 /* SWREG80_ERROR_REF_Y_HOR_VIRSTRIDE */ 50 RK_U32 reg80_error_ref_hor_virstride; 51 52 /* SWREG81_ERROR_REF_UV_HOR_VIRSTRIDE */ 53 RK_U32 reg81_error_ref_raster_uv_hor_virstride; 54 55 /* SWREG82_ERROR_REF_Y_VIRSTRIDE */ 56 RK_U32 reg82_error_ref_virstride; 57 58 /* SWREG83_REF0_Y_HOR_VIRSTRIDE */ 59 RK_U32 reg83_ref0_hor_virstride; 60 61 /* SWREG84_REF0_UV_HOR_VIRSTRIDE */ 62 RK_U32 reg84_ref0_raster_uv_hor_virstride; 63 64 /* SWREG85_REF0_Y_VIRSTRIDE */ 65 RK_U32 reg85_ref0_virstride; 66 67 /* SWREG86_REF1_Y_HOR_VIRSTRIDE */ 68 RK_U32 reg86_ref1_hor_virstride; 69 70 /* SWREG87_REF1_UV_HOR_VIRSTRIDE */ 71 RK_U32 reg87_ref1_raster_uv_hor_virstride; 72 73 /* SWREG88_REF1_Y_VIRSTRIDE */ 74 RK_U32 reg88_ref1_virstride; 75 76 /* SWREG89_REF2_Y_HOR_VIRSTRIDE */ 77 RK_U32 reg89_ref2_hor_virstride; 78 79 /* SWREG90_REF2_UV_HOR_VIRSTRIDE */ 80 RK_U32 reg90_ref2_raster_uv_hor_virstride; 81 82 /* SWREG91_REF2_Y_VIRSTRIDE */ 83 RK_U32 reg91_ref2_virstride; 84 85 /* SWREG92_REF3_Y_HOR_VIRSTRIDE */ 86 RK_U32 reg92_ref3_hor_virstride; 87 88 /* SWREG93_REF3_UV_HOR_VIRSTRIDE */ 89 RK_U32 reg93_ref3_raster_uv_hor_virstride; 90 91 /* SWREG94_REF3_Y_VIRSTRIDE */ 92 RK_U32 reg94_ref3_virstride; 93 94 /* SWREG95_REF4_Y_HOR_VIRSTRIDE */ 95 RK_U32 reg95_ref4_hor_virstride; 96 97 /* SWREG96_REF4_UV_HOR_VIRSTRIDE */ 98 RK_U32 reg96_ref4_raster_uv_hor_virstride; 99 100 /* SWREG97_REF4_Y_VIRSTRIDE */ 101 RK_U32 reg97_ref4_virstride; 102 103 /* SWREG98_REF5_Y_HOR_VIRSTRIDE */ 104 RK_U32 reg98_ref5_hor_virstride; 105 106 /* SWREG99_REF5_UV_HOR_VIRSTRIDE */ 107 RK_U32 reg99_ref5_raster_uv_hor_virstride; 108 109 /* SWREG100_REF5_Y_VIRSTRIDE */ 110 RK_U32 reg100_ref5_virstride; 111 112 /* SWREG101_REF6_Y_HOR_VIRSTRIDE */ 113 RK_U32 reg101_ref6_hor_virstride; 114 115 /* SWREG102_REF6_UV_HOR_VIRSTRIDE */ 116 RK_U32 reg102_ref6_raster_uv_hor_virstride; 117 118 /* SWREG103_REF6_Y_VIRSTRIDE */ 119 RK_U32 reg103_ref6_virstride; 120 121 /* SWREG104_REF7_Y_HOR_VIRSTRIDE */ 122 RK_U32 reg104_ref7_hor_virstride; 123 124 /* SWREG105_REF7_UV_HOR_VIRSTRIDE */ 125 RK_U32 reg105_ref7_raster_uv_hor_virstride; 126 127 /* SWREG106_REF7_Y_VIRSTRIDE */ 128 RK_U32 reg106_ref7_virstride; 129 130 } Vdpu383RegAvs2dParas; 131 132 typedef struct Vdpu383RegAvs2dAddr_t { 133 /* SWREG168_DECOUT_BASE */ 134 RK_U32 reg168_decout_base; 135 136 /* SWREG169_ERROR_REF_BASE */ 137 RK_U32 reg169_error_ref_base; 138 139 /* SWREG170_185_REF0_BASE */ 140 RK_U32 reg170_185_ref_base[16]; 141 142 RK_U32 reserve_reg186_191[6]; 143 144 /* SWREG192_PAYLOAD_ST_CUR_BASE */ 145 RK_U32 reg192_payload_st_cur_base; 146 147 /* SWREG193_FBC_PAYLOAD_OFFSET */ 148 RK_U32 reg193_fbc_payload_offset; 149 150 /* SWREG194_PAYLOAD_ST_ERROR_REF_BASE */ 151 RK_U32 reg194_payload_st_error_ref_base; 152 153 /* SWREG195_210_PAYLOAD_ST_REF0_BASE */ 154 RK_U32 reg195_210_payload_st_ref_base[16]; 155 156 RK_U32 reserve_reg211_215[5]; 157 158 /* SWREG216_COLMV_CUR_BASE */ 159 RK_U32 reg216_colmv_cur_base; 160 161 /* SWREG217_232_COLMV_REF0_BASE */ 162 RK_U32 reg217_232_colmv_ref_base[16]; 163 164 } Vdpu383RegAvs2dAddr; 165 166 typedef struct Vdpu383Avs2dRegSet_t { 167 Vdpu383RegVersion reg_version; /* 0 */ 168 Vdpu383CtrlReg ctrl_regs; /* 8-30 */ 169 Vdpu383RegCommonAddr common_addr; /* 128-134, 140-161 */ 170 Vdpu383RegAvs2dParas avs2d_paras; /* 64-74, 80-106 */ 171 Vdpu383RegAvs2dAddr avs2d_addrs; /* 168-185, 192-210, 216-232 */ 172 } Vdpu383Avs2dRegSet; 173 174 #endif /* __VDPU34X_H264D_H__ */ 175