906             hw_regs->ctrl_regs.reg9.dpb_data_sel = 0;  in hal_h265d_vdpu384a_gen_regs()
907             hw_regs->ctrl_regs.reg9.dpb_output_dis = 0;  in hal_h265d_vdpu384a_gen_regs()
908             hw_regs->ctrl_regs.reg9.pp_m_output_mode = 0;  in hal_h265d_vdpu384a_gen_regs()
915             hw_regs->ctrl_regs.reg9.dpb_data_sel = 1;  in hal_h265d_vdpu384a_gen_regs()
916             hw_regs->ctrl_regs.reg9.dpb_output_dis = 1;  in hal_h265d_vdpu384a_gen_regs()
917             hw_regs->ctrl_regs.reg9.pp_m_output_mode = 2;  in hal_h265d_vdpu384a_gen_regs()
931             hw_regs->ctrl_regs.reg9.dpb_data_sel = 1;  in hal_h265d_vdpu384a_gen_regs()
932             hw_regs->ctrl_regs.reg9.dpb_output_dis = 1;  in hal_h265d_vdpu384a_gen_regs()
933             hw_regs->ctrl_regs.reg9.pp_m_output_mode = 1;  in hal_h265d_vdpu384a_gen_regs()
1012     hw_regs->ctrl_regs.reg8_dec_mode = 0; // hevc  in hal_h265d_vdpu384a_gen_regs()
1013     hw_regs->ctrl_regs.reg9.low_latency_en = 0;  in hal_h265d_vdpu384a_gen_regs()
1015     hw_regs->ctrl_regs.reg10.strmd_auto_gating_e      = 1;  in hal_h265d_vdpu384a_gen_regs()
1016     hw_regs->ctrl_regs.reg10.inter_auto_gating_e      = 1;  in hal_h265d_vdpu384a_gen_regs()
1017     hw_regs->ctrl_regs.reg10.intra_auto_gating_e      = 1;  in hal_h265d_vdpu384a_gen_regs()
1018     hw_regs->ctrl_regs.reg10.transd_auto_gating_e     = 1;  in hal_h265d_vdpu384a_gen_regs()
1019     hw_regs->ctrl_regs.reg10.recon_auto_gating_e      = 1;  in hal_h265d_vdpu384a_gen_regs()
1020     hw_regs->ctrl_regs.reg10.filterd_auto_gating_e    = 1;  in hal_h265d_vdpu384a_gen_regs()
1021     hw_regs->ctrl_regs.reg10.bus_auto_gating_e        = 1;  in hal_h265d_vdpu384a_gen_regs()
1022     hw_regs->ctrl_regs.reg10.ctrl_auto_gating_e       = 1;  in hal_h265d_vdpu384a_gen_regs()
1023     hw_regs->ctrl_regs.reg10.rcb_auto_gating_e        = 1;  in hal_h265d_vdpu384a_gen_regs()
1024     hw_regs->ctrl_regs.reg10.err_prc_auto_gating_e    = 1;  in hal_h265d_vdpu384a_gen_regs()
1026     hw_regs->ctrl_regs.reg11.rd_outstanding = 32;  in hal_h265d_vdpu384a_gen_regs()
1027     hw_regs->ctrl_regs.reg11.wr_outstanding = 250;  in hal_h265d_vdpu384a_gen_regs()
1030     hw_regs->ctrl_regs.reg16.error_proc_disable = 1;  in hal_h265d_vdpu384a_gen_regs()
1031     hw_regs->ctrl_regs.reg16.error_spread_disable = 0;  in hal_h265d_vdpu384a_gen_regs()
1032     hw_regs->ctrl_regs.reg16.roi_error_ctu_cal_en = 0;  in hal_h265d_vdpu384a_gen_regs()
1034     hw_regs->ctrl_regs.reg20_cabac_error_en_lowbits = 0xffffffff;  in hal_h265d_vdpu384a_gen_regs()
1035     hw_regs->ctrl_regs.reg21_cabac_error_en_highbits = 0x3ff3f9ff;  in hal_h265d_vdpu384a_gen_regs()
1037     hw_regs->ctrl_regs.reg13_core_timeout_threshold = 0xffff;  in hal_h265d_vdpu384a_gen_regs()
1072                     hw_regs->ctrl_regs.reg16.error_proc_disable = 1;  in hal_h265d_vdpu384a_gen_regs()
1130     vdpu384a_setup_statistic(&hw_regs->ctrl_regs);  in hal_h265d_vdpu384a_gen_regs()
1155 …vdpu384a_setup_down_scale(mframe, reg_ctx->dev, &hw_regs->ctrl_regs, (void*)&hw_regs->h265d_paras);  in hal_h265d_vdpu384a_gen_regs()
1159 …vdpu384a_setup_down_scale(mframe, reg_ctx->dev, &hw_regs->ctrl_regs, (void*)&hw_regs->h265d_paras);  in hal_h265d_vdpu384a_gen_regs()
1163             hw_regs->ctrl_regs.reg9.scale_down_en = 0;  in hal_h265d_vdpu384a_gen_regs()
1210         wr_cfg.reg = &hw_regs->ctrl_regs;  in hal_h265d_vdpu384a_start()
1211         wr_cfg.size = sizeof(hw_regs->ctrl_regs);  in hal_h265d_vdpu384a_start()
1246         rd_cfg.reg = &hw_regs->ctrl_regs.reg15;  in hal_h265d_vdpu384a_start()
1247         rd_cfg.size = sizeof(hw_regs->ctrl_regs.reg15);  in hal_h265d_vdpu384a_start()
1299         (!hw_regs->ctrl_regs.reg15.rkvdec_frame_rdy_sta) ||  in hal_h265d_vdpu384a_wait()
1300         hw_regs->ctrl_regs.reg15.rkvdec_strm_error_sta ||  in hal_h265d_vdpu384a_wait()
1301         hw_regs->ctrl_regs.reg15.rkvdec_core_timeout_sta ||  in hal_h265d_vdpu384a_wait()
1302         hw_regs->ctrl_regs.reg15.rkvdec_ip_timeout_sta ||  in hal_h265d_vdpu384a_wait()
1303         hw_regs->ctrl_regs.reg15.rkvdec_bus_error_sta ||  in hal_h265d_vdpu384a_wait()
1304         hw_regs->ctrl_regs.reg15.rkvdec_buffer_empty_sta ||  in hal_h265d_vdpu384a_wait()
1305         hw_regs->ctrl_regs.reg15.rkvdec_colmv_ref_error_sta) {  in hal_h265d_vdpu384a_wait()