238     Vdpu383CtrlReg *ctrl_regs = &regs->ctrl_regs;  in init_ctrl_regs()  local
240     ctrl_regs->reg8_dec_mode = 3;  // AVS2  in init_ctrl_regs()
241     ctrl_regs->reg9.buf_empty_en = 1;  in init_ctrl_regs()
243     ctrl_regs->reg10.strmd_auto_gating_e      = 1;  in init_ctrl_regs()
244     ctrl_regs->reg10.inter_auto_gating_e      = 1;  in init_ctrl_regs()
245     ctrl_regs->reg10.intra_auto_gating_e      = 1;  in init_ctrl_regs()
246     ctrl_regs->reg10.transd_auto_gating_e     = 1;  in init_ctrl_regs()
247     ctrl_regs->reg10.recon_auto_gating_e      = 1;  in init_ctrl_regs()
248     ctrl_regs->reg10.filterd_auto_gating_e    = 1;  in init_ctrl_regs()
249     ctrl_regs->reg10.bus_auto_gating_e        = 1;  in init_ctrl_regs()
250     ctrl_regs->reg10.ctrl_auto_gating_e       = 1;  in init_ctrl_regs()
251     ctrl_regs->reg10.rcb_auto_gating_e        = 1;  in init_ctrl_regs()
252     ctrl_regs->reg10.err_prc_auto_gating_e    = 1;  in init_ctrl_regs()
254     ctrl_regs->reg13_core_timeout_threshold = 0xffffff;  in init_ctrl_regs()
256     ctrl_regs->reg16.error_proc_disable = 1;  in init_ctrl_regs()
257     ctrl_regs->reg16.error_spread_disable = 0;  in init_ctrl_regs()
258     ctrl_regs->reg16.roi_error_ctu_cal_en = 0;  in init_ctrl_regs()
260     ctrl_regs->reg20_cabac_error_en_lowbits = 0xffffffff;  in init_ctrl_regs()
261     ctrl_regs->reg21_cabac_error_en_highbits = 0x3fffffff;  in init_ctrl_regs()
264     ctrl_regs->reg28.axi_perf_work_e = 1;  in init_ctrl_regs()
265     ctrl_regs->reg28.axi_cnt_type = 1;  in init_ctrl_regs()
266     ctrl_regs->reg28.rd_latency_id = 0xb;  in init_ctrl_regs()
267     ctrl_regs->reg28.rd_latency_thr = 0;  in init_ctrl_regs()
269     ctrl_regs->reg29.addr_align_type = 2;  in init_ctrl_regs()
270     ctrl_regs->reg29.ar_cnt_id_type = 0;  in init_ctrl_regs()
271     ctrl_regs->reg29.aw_cnt_id_type = 0;  in init_ctrl_regs()
272     ctrl_regs->reg29.ar_count_id = 0xa;  in init_ctrl_regs()
273     ctrl_regs->reg29.aw_count_id = 0;  in init_ctrl_regs()
274     ctrl_regs->reg29.rd_band_width_mode = 0;  in init_ctrl_regs()
386             regs->ctrl_regs.reg9.fbc_e = 1;  in fill_registers()
391             regs->ctrl_regs.reg9.tile_e = 1;  in fill_registers()
395             regs->ctrl_regs.reg9.fbc_e = 0;  in fill_registers()
396             regs->ctrl_regs.reg9.tile_e = 0;  in fill_registers()
487             vdpu383_setup_down_scale(mframe, p_hal->dev, &regs->ctrl_regs,  in fill_registers()
490             regs->ctrl_regs.reg9.scale_down_en = 0;  in fill_registers()
702     vdpu383_setup_statistic(&regs->ctrl_regs);  in hal_avs2d_vdpu383_gen_regs()
736         wr_cfg.reg = &regs->ctrl_regs;  in hal_avs2d_vdpu383_start()
737         wr_cfg.size = sizeof(regs->ctrl_regs);  in hal_avs2d_vdpu383_start()
772         rd_cfg.reg = &regs->ctrl_regs.reg15;  in hal_avs2d_vdpu383_start()
773         rd_cfg.size = sizeof(regs->ctrl_regs.reg15);  in hal_avs2d_vdpu383_start()
909     AVS2D_HAL_TRACE("read irq_status 0x%08x\n", regs->ctrl_regs.reg19);  in hal_avs2d_vdpu383_wait()
917         if ((!regs->ctrl_regs.reg15.rkvdec_frame_rdy_sta) ||  in hal_avs2d_vdpu383_wait()
918             regs->ctrl_regs.reg15.rkvdec_strm_error_sta ||  in hal_avs2d_vdpu383_wait()
919             regs->ctrl_regs.reg15.rkvdec_core_timeout_sta ||  in hal_avs2d_vdpu383_wait()
920             regs->ctrl_regs.reg15.rkvdec_ip_timeout_sta ||  in hal_avs2d_vdpu383_wait()
921             regs->ctrl_regs.reg15.rkvdec_bus_error_sta ||  in hal_avs2d_vdpu383_wait()
922             regs->ctrl_regs.reg15.rkvdec_buffer_empty_sta ||  in hal_avs2d_vdpu383_wait()
923             regs->ctrl_regs.reg15.rkvdec_colmv_ref_error_sta)  in hal_avs2d_vdpu383_wait()
935     memset(&regs->ctrl_regs.reg19, 0, sizeof(RK_U32));  in hal_avs2d_vdpu383_wait()